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PHY Interface

Sharath M
Prodigy 30 points
Other Parts Discussed in Thread: DP83848K

Hi,

We are using DP83848K PHY for ethernet communication. The PHY is interfaced to Blackfin 518 processor and is configured to work in MII mode.

Currently we are facing few issues. The PHY CLKIN being 25 MHz we are expected to get clock in TX_CLK and RX_CLK pinouts from the PHY which is not happening.

But from the drivers we are able to establish link between processor and PHY i.e, we are able to read the PHYID register 1 & 2 throuch SMI. But we are unable to get any clock on TX_CLK/RX_CLK pin. Can u please suggest what we might be doing wrong and I have attached PHY interface schematics that we are using.

Thanks in advancePHY.rar

  • 0
    TI__Mastermind 19780 points
    Hi Sharath,

    Please verify that you can establish a link with another PHY across the RJ45.

    Thank you for your schematic. Do you have any decoupling on the IOVDD and AVDD supplies?

    Can you also dump your register set, from address 0x0 to 0x1F?

    Regards,
  • 0 in reply to Rob Rodrigues
    Prodigy 30 points

    Hi rob,

    Yes we have decoupling on IOVDD and AVDD supplies.

    The following are the register contents read:

    phy_regs[0]=3500
    phy_regs[1]=786d
    phy_regs[2]=2000
    phy_regs[3]=5c90
    phy_regs[4]=1e1
    phy_regs[5]=c1e1
    phy_regs[6]=d
    phy_regs[7]=2801
    phy_regs[8]=0
    phy_regs[9]=0
    phy_regs[a]=0
    phy_regs[b]=0
    phy_regs[c]=0
    phy_regs[d]=0
    phy_regs[e]=0
    phy_regs[f]=0
    phy_regs[10]=615
    phy_regs[11]=0
    phy_regs[12]=0
    phy_regs[13]=0
    phy_regs[14]=0
    phy_regs[15]=0
    phy_regs[16]=100
    phy_regs[17]=1
    phy_regs[18]=0
    phy_regs[19]=8020
    phy_regs[1a]=804
    phy_regs[1b]=0
    phy_regs[1c]=0
    phy_regs[1d]=6011
    phy_regs[1e]=83e
    phy_regs[1f]=0

    Regards,

    Sharath

  • 0 in reply to Sharath M
    TI__Mastermind 19780 points
    Hi Sharath,

    Your PHY is in MII isolate mode, as indicated by bit 10 in address 0x00

    In MII isolate mode, you will not receive a clock out. This could be caused by an external pull-down on the COL pin. A pull-down on the COL pin will set the PHY address to 0x0 and put the device in MII isolate.

    Clear the MII isolate bit.

    Regards,
  • 0 in reply to Rob Rodrigues
    Prodigy 30 points

    Hi rob,

    Thanks for the solution , i am able get TX and RX clocks after removing the pulldown at COL pin.

    Regards,

    Sharath