DP83867CR frame loss and CRC error with certain frames sizes

What's your clock source?  If it's an oscillator, maybe you have an issue with jitter?

Hi Aniruddha,

The issue seems to be independent of the ethernet cable length and whether the PHY is in master or slave mode. But it need to be in 1G mode.

I have tested with PRBS payload and fixed payload and the issue is not dependent on the payload.         

We notice some CRC errors on our systems, so I began the debug on only one system. I have only verified the 65 byte issue on one system. I will verify whether the other system also have the issue with 65 byte frames with 95% load tomorrow.

The 25 MHz clock is from a TCXO. I have tried to change the clock source to a SI5344 but I did not see any change in the PHY behavior.

I have verified the clock output signal from the PHY in order to verify the clock inside the PHY.

Regards Sune

Hi

I have verified that the issue is also exist on another board, so it is unfortunately not just a single device defect.
I have measured the jitter on the output clock from the PHY. Thereby I can measure the reference clock that the PHY see.
The 25Mhz clock out of the PHY has a Cycle-Cycle jitter RMS jitter of 34 ps and N-cycle jitter RMS jitter of 23 ps, see plot below.
I have also measured the receive clock for Channel A and I can’t see any issue with the receive clock. A plot of the measurement is bewlo .
I tried to measure the error rate with difference frame size, see list below. 
Notice the pattern in the frame size where I see the issue:

- 65 Byte frames bit error rate  3.0 x 10^-9
- 73 Byte frames bit error rate  2.2 x 10^-9 
- 81 Byte frames bit error rate  3.6 x 10^-9
- 89 Byte frames bit error rate  3.0 x 10^-9
- 97 Byte frames No error

Regards Sune

Hi Aniruddha 

I also see the 65 bytes frame issue on the Texas Instruments evaluation board “DP83867IRPAP-EVM”.

Below are the MDIO commands send to the board:

Notice, in my setup I see the issue regardless of the loopback.

Please check my setup below and comment on next step in the debug process.

#Reset all registers (and not just IEEE registers using BMCR bit15)

MDIO_write(0x001F, 0x8000)

Sleep 100ms

#Enable Auto-Negotiation and FDX =1

MDIO_write(0x0000, 1<<12 | 1<<8)

# ANEG_RESTART=1

MDIO_write(0x0000, 1<<12 | 1<<9 | 1<<8)

#Setup PHY for normal operation and auto MDIX

MDIO_write(0x0010, 0x5048)

#Enable loopback

MDIO_write(0x00EF, 0xE720)

#Soft reset after changing LOOPCR

MDIO_write(0x001F, 0x4000)

#Enable reverse loopback (MDI RX to TX)

MDIO_write(0x0016, 0x8 << 2)

Regards Sune

Hi Aniruddha

I agree the PHY can operat with 100% utilization just the IPG is not under 12 byte.

Please try a test with just two 65 byte frames and a IPG between the frames of 10 to 8 byte.

I have attached the schematic part with the DP83867CR , but I see the schematic as irrelevant as I see the same issue on the TI evaluation module DP83867IRPAP-EVM.

Regards Sune

Have you reproduced the issue with two 65 byte frames and a IPG between the two frames of 8 byte?