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TCA9517 A- B- Side differences

SSF
Intellectual 2025 points
Other Parts Discussed in Thread: P82B96, TCA9517

Hi Team,

My customer was using the TCA9517 along with the P82B96 and were having issues cascading the two. In short, due to their logic levels, they had to turn the device around by swapping the A-side and B-sides of the device in their circuit.

They have some questions around the circuit and application of the device they would like to get some clarity on to ensure they are using the device correctly:

- Why do the A-side and B-side interfaces on the device behave differently
- They are now using the device with the B-side to the master I2C. Is this an acceptable solution? Are there any downsides to this? The datasheet seems to recommend that the A-side is on the I2C master bus.

Thanks in advance for the help here. Below is the original issue they were having:


Regards,
Steve

  • 0
    TI__Genius 16550 points
    Hello Steve,

    You are correct that the A and B sides are different.

    This is actually very common across the industry with buffered translators for i2C. It is required because the device cannot detect its own low as an external low if that makes sense.

    Consider the following:
    1) Both sides are high. Master is on A side, slave is on B side.
    2) Master on A side pulls the bus low.
    3) Repeater will detect A side is low and pull B side low
    4) Repeater sees a low on the B-side and assumes it's the slave pulling low. It will pull down on the A side (with its own internal driver)
    5) Master on A side releases the bus, but it never goes high because A side is being pulled low by repeater.
    6) Bus is stuck low.


    To get around this situation, the repeaters implement what's called a static voltage offset on 1 of the sides (most buffered translators will put this on the higher voltage side, most commonly the B side). This means that the output on the B side is forced to be about 50 mV higher than the input low-threshold. For example on the TCA9517, the VOL is ~0.5V, and the VILC is ~0.45V. This means that when the device transmits a low on the B side at 0.5V, it won't trip the 0.45V input threshold, and the bus doens't get stuck.


    The problems with this type of implementation is that some devices can no longer be connected together due to the VOL/VIL mis match, which is exactly what you're experiencing.



    To answer your other question:
    It is perfectly acceptable to have the master on the B side, there is no requirement on what side the master is on.