When performing a hardware reset of the DP83867, is there any requirements apart from what is described in the datasheet?
In our hardware, I have an FPGA driving the phy. The only way I can get the phy to work is to keep the RESET_N constantly deasserted(high). If try and assert the reset, wait unti the X_I clock is running , the phy never comes out of reset and I cannot talk to it over the MDIO interface
I get the feeling that some other inputs to the PHY are important for bringing it out of reset but I can't figure out what.
