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PDB time delay for TI Serializer part DS90UB913A-Q1

Narasimha LV
Prodigy 130 points

  1. PDB delay in Serializer DS90UB913A-Q1.msgWe are connecting VDDIO & VDD_n  on same voltage rail i.e. 1.8V so both ramp up at the same time (basically t1 is zero)

  2. PDB signal should come after the VDD_n supply is ramped up, but why there is maximum limit for this time parameter (t2)?

  3. As marked in datasheet  figure 27,  why t2 reference is taken with PDB signal (in the time parameter description, it is mentioned as rise time for VDD_n)?

    4. Please confirm what is the  minimum and Maxim  PDB delay after VDD_n is stable.

     

Regards,

Narasimha LV

  • 0
    TI__Intellectual 2000 points

    Hello Narasimha,

    The t2 is the VDD_n rise time, so it does not influence PDB at all. PDB must be rumped up after both VDDIO and VDD_n are stable. The delay is not decided and you can rump up PDB at any time AFTER VDDIO and VDD_n are stable (1.8V in your case). I attached a figure below.

    Best regards,
    Ryosuke