SNx5DP159 - Question on REFCLK_OUT in Display Port Application

Mizanur Chowdhury

Hello Team,

In Display Port Application following the apps note SLLA358, section 4.5, one can generate a REFCLK_OUT using the SNx5DP159 part. This signal is generated form the DisplayPort Link Rate. A DP signal can have 1,2 or 4 lanes. Could you tell me how the REFCLK_OUT is generated? Is it related to a dedicated DP lane or is it variable.

The reason of this question is that following the Displayport specification in case of disturbance or break on a specific lane it will be switched to another lane automatically.

So the question is if the DP159 is compliant to this specification. That means if e.g. lane 0 is generating the clock and this lane will break. Will the part automatically switch to another lane or not.

Thanks for your inputs on this.

Best regards,

Mizanur

over 8 years ago

0 Moises Garcia over 8 years ago

TI__Mastermind 23815 points

HI Mizanur,

REFCLK_OUT is generated from the clock recovered in Lane 0.
Lane 0 is the only lane that is active when using 1, 2 or 4 lanes.
If any of the lanes brakes, the receiver wouldn't be able to recover the video, it could switch to a lower lane count, which will always include lane 0.

Regards

0 Mizanur Chowdhury over 8 years ago in reply to Moises Garcia

TI__Genius 17270 points

Hi Moises,
Many thanks for the quick reply.

Best regards,
Mizanur

0 Mizanur Chowdhury over 8 years ago in reply to Moises Garcia

TI__Genius 17270 points

Hello Moises,

Customer asked what happens if Lane0 breaks?

Best regards,

Mizanur

0 Moises Garcia over 8 years ago in reply to Mizanur Chowdhury

TI__Mastermind 23815 points

Hi Mizanur,

In redriver/retimer mode if lane0 breaks there won't be any video, and you won't be able to reduce lane count because all modes use lane0

In retimer mode If lane0 breaks DP159 will lose lock.

Regards

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SNx5DP159 - Question on REFCLK_OUT in Display Port Application