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TLK105 RESET Pin

Ethan Held22
Prodigy 680 points
Other Parts Discussed in Thread: TLK105

Hi All, 

I had a question on the TLK105.  I’m using the TLK105 PHY on my board and I’m concerned about the RESET pin on it. I’m using a 2.2k resistor to pull up the pin and depending on the internal POR feature per section 6 of the datasheet. Is the requirement of a stable clock for at least one microsecond before the RESET is de asserted applicable here? My colleagues have run into some issues with the power on reset, but they are clocking from an FPGA and I am clocking from an on board oscillator. Does the pin need to floated if it isn’t necessarily used?

Thanks for your insight on this!

Ethan

T
Ethanhat is odd because the datasheet does not even specify a minimum clock frequency, only a Max.
 
I was envisioning a scenario where each DAC is sampling at 150MSPS using a 150MHz clock, 1X interpolation. The is 150MSPS*16bit*(10/8) * 4 Converters = 12 Gbps. This is still less than the 12.5Gbps/lane max.
  • 0
    TI__Mastermind 19780 points
    Hi Ethan,

    I think the last part of your post is in error so I will ignore this unless you later clarify.

    When using a crystal, you wont run into issues with the timing of POR of the TLK105. You can tie the RESET pin high.

    When an external source provides XI, then there is the chance during POR there could be no reference which can cause the PHY to become unresponsive.

    Best Regards,