Hello,
I am trying to stream 8bit and 10bit YUV422 @ 30fps from an ISP and '913 to '914. The 8bit YUV422 works well, but 10bit rarely (extremely rarely) works, and if it does it is for a few frames (half of which are dropped) or around 1 minute.
On the '914 side, I am currently seeing what appears to be a cycle skip in PCLK followed by an increase in PCLK frequency up to ~96MHz and finally a loss of LOCK. On the '913 side, the PCLK appears very stable. The pair is in 12b HF External Clock mode with a 48MHz external oscillator on GPO3 of the '913. We expect the period of the PCLK to be: inv(48*1.5) = 13.8ns. See the following wave forms for more clarification:
In this shot, Ch. 3 is PCLK on the '913 side with the sensor/ISP, Ch. 2 is PCLK on the '914 side, Ch. 1 is LOCK and Ch. 4 is PASS. Notice that the PCLK on the '913 side is still running. The next screenshot will show the PCLK on the '913 side compared with the PCLK on the '914 side:
Notice that the PCLK on the '913 side is still the expected 72MHz, but on the '914 side it is much faster (~108 MHz). Then the PCLK on the '914 side stops, followed by the loss of LOCK. The next waveform shows the transition of PCLK on the '914 side from the 72MHz up to ~108MHz:
In the above shot, notice the point in the '914 PCLK waveform at which it should be going low, but goes back up to an even higher amplitude than before. At this point, the PCLK has jumped from 72MHz to 108MHz:
Have you seen this behavior before? The PCLK coming from the ISP does not appear to have much jitter, not even close to the 1*T period of allowable jitter in EXT CLK mode. I have been chasing this around my circuits power rails to see if there is some event leading up to this, but I cannot seem to find anything. I have also looked at the PoC caps, and there is row rate noise, but nothing drastic leading up to this point:
I have also checked all data bits in both modes (8- and 10-bit modes on the ISP) to make sure there was data coming through along with the other sync signals (PCLK, HSYNC and VSYNC), and there was data coming through as expected for both. Could it be that when the device receives 10bits of data it will automatically transition from one mode to another (12 to 10)? Any guidance here is very appreciated.
Sincerely,
Luis
