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DS110DF410 reset bit issue

Hello,

Do you have any comments for reset bit not working issue? 

1) Per document, reg04 bit6 is self-clearing bit. but it doesn't self-clear after set it on.
2) All other config doesn't reset to factory default.
 



 
DIAG>i2cwrite 0 0 2 0x18 0xff 1 0x0c 1
DIAG>i2cread 0 0 2  0x18 0x00 1 48
0x00 0x00 0xdc 0xc0 0x00 0x00 0x00 0x00 0x00 0x00 0x10 0x0f 0x08 0x00 0x93 0x69
0x3a 0x20 0xa0 0x30 0x00 0x10 0x7a 0x36 0x40 0x23 0x00 0x03 0x24 0x00 0xe9 0x55
0x00 0x00 0x00 0x40 0x00 0x00 0x00 0x35 0x68 0x20 0x30 0x00 0x72 0x80 0x00 0x06

DIAG>i2cwrite 0 0 2 0x18 0x09 1 0x20 1
DIAG>i2cwrite 0 0 2 0x18 0x1e 1 0x01 1
8DIAG>i2cwrite 0 0 2 0x18 0x3f 1 0x80 1
DIAG>i2cwrite 0 0 2 0x18 0x31 1 0x00 1
DIAG>i2cwrite 0 0 2 0x18 0x2d 1 0x87 1
DIAG>i2cwrite 0 0 2 0x18 0x2f 1 0x04 1
DIAG>i2cwrite 0 0 2 0x18 0x3a 1 0x0 1
DIAG>i2cread 0 0 2  0x18 0x00 1 48
0x00 0x11 0xdc 0x80 0x00 0x00 0x00 0x00 0x00 0x20 0x10 0x0f 0x08 0x00 0x93 0x69
0x3a 0x20 0xa0 0x30 0x00 0x10 0x7a 0x36 0x40 0x23 0x00 0x03 0x24 0x00 0x01 0x55
0x00 0x00 0x00 0x40 0x00 0x00 0x00 0x28 0x84 0x40 0x30 0x00 0x72 0x87 0x00 0x04

/* set Reg4 bit 6 */
DIAG>i2cwrite 0 0 2 0x18 0x4 1 0x40 1
DIAG>i2cread 0 0 2  0x18 0x00 1 48
0x00 0x00 0xdc 0x80
0x40 0x00 0x00 0x00 0x00 0x20 0x10 0x0f 0x08 0x00 0x93 0x69
0x3a 0x20 0xa0 0x30 0x00 0x10 0x7a 0x36 0x40 0x23 0x00 0x03 0x24 0x00 0x01 0x55
0x00 0x00 0x00 0x40 0x00 0x00 0x00 0x28 0x81 0x40 0x30 0x00 0x72 0x87 0x00 0x04

DIAG>

BR

Patrick

  • Hi Patrick,

    Sorry for the delay in response. We are looking into this and will get back to you soon.

    Regards,

    Michael
  • The shared registers reset works; we've confirmed it via lab experiments. Please however do make sure that you are resetting 0x04 of the shared registers

    • Bit 2 of register 0xff is used to select either the control/shared registers set or a channel registers set. If bit 2 of register 0xff is cleared (written with a 0), then all subsequent read and write operations over the SMBus are directed to the control/shared registers

    • Shared register 0x04[6] resets the share registers. This bit is self-clearing, and sets the shared registers back to their default settings. It does not reset the channel registers back to their default settings.
    • On the other hand, to reset channel registers, you would need to first set 0xFF[2]=1, then select the desired channel via 0xFF[1:0]. Then, you can set 0x0[2]=1 to reset the channel registers

    Cordially,

    Rodrigo Natal

    DPS Applications Engineer