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SN65DSI84 rush current

NAOKI AOYAMA
Guru 11215 points

Hello,

Our customer observe a rush current when the EN pin Low to High.

The rush current flow 600mA for 5usec.

The customer did not configure LP11 mode when the EN pin Low to High.

Is it a wrong setting?

Best Regards,

Naoki Aoyama

  • 0
    TI__Mastermind 18655 points

    Hello Naoki, 

    It is required by the MIPI spec for the host to drive DSI outputs to LP11 prior to the transition to the HS mode. The initialization/transition sequence requirement is per the MIPI DPHY (Section 6.11) and DSI (Section 5.7) spec requirements.

    If DSI interface is driven to illegal states/protocol by the host, the DSI84 may get into undesirable states:
    - DSI clock or data termination enable may get "stuck"
    - DSI clock does not get enabled internally correctly

    Unexpected behavior may occur when the EN is asserted(transition from 0 to 1) while DSI CLK = LP00.
    The DSI_CLK/DATA should be provided per the recommended initialization sequence (init seq5, Figure 6)

    Regards

  • 0 in reply to Joel Jimenez0
    Guru 11215 points
    Hello Joel,

    Thank you for your reply.
    I see. I will suggest the customer DSI CLK and DATA LP11 when the EN is asserted.

    May I ask one more question?
    In the figure 6 on the DS P12, the DSI DATA and CLK transition to LP00 as same timing.
    Is this timing correct? Is it needed a delay time each other?

    Best Regards,
    Naoki Aoyama
  • 0 in reply to NAOKI AOYAMA
    TI__Mastermind 18655 points

    Hello Naoki, 

    You can refer to the Table 2 (Recommended Initialization Sequence) which states that after the EN pin is asserted, you have to wait for 1ms then initialize the CSR registers and start the DSI video stream, that is to say, transmit DSI Data and DSI Clock.

    Regards

  • 0 in reply to Joel Jimenez0
    Guru 11215 points
    Hello Joel,

    Thank you for your reply.

    Thanks,
    Naoki Aoyama