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SN65DSI84 - output data during init seq 1 to init seq 8

Hirotaka Matsumoto
Guru 27595 points

Other Parts Discussed in Thread: SN65DSI84

Hi all

Would you mind if we ask SN65DSI84?

During init seq 1 to init seq 8, is there possibility which the output data is indefinite?
Or, until Init seq8 finishes, there is no output, right?

Kind regards,

Hirotaka Matsumoto

  • 0
    TI__Mastermind 18655 points
    Hello Matsumoto-san,
    LVDS CLK/data could be undeterminaded only before asserting (low) the EN terminal. When EN terminal is asserted LVDS CLK/data will be low and the LVDS CLK would start toggling as soon as PLL_EN = 1. When PLL_Lock =1, the LVDS_CLK is output at a programmed frequency.

    "Other LVDS CLK/data lanes stay low until they are configured to be enabled in corresponding CSRs” is for the LVDS outputs not configured to be enabled. if the CHA_24BPP_MODE is configured for 18bpp, the A_Y3P/N is disabled therefore the A_Y3P/N should stay low.

    Regards