I am working on a Xilinx Spartan6 LX45 interfacing to the TUSB9261 using SATA-I right now.
The LX45 is emulating a SATA HDD. This is working and the HDD design is functioning.
However, at startup I am seeing the initial link between the LX45 and TUSB fail once out of every 3 or 4 boot cycles.
At boot, the LX45 sends the HDD Signature Packet to the TUSB9261. The TUSB9261 then responds with an RERR primitive. If I keep sending the HDD Signature, the TUSB9261 keeps sending me RERR and then it won't even send an RRDY to allow my SATA core to begin the transmission of signature data.
I have a loop now where I reset the TUSB9261 and try again. Sometimes it takes 5 or 6 reset cycles before I get a good link (i.e. the TUSB9261 responds with an ROK primitive). Once i get the ROK from the 9261, I don't ever see any other trouble on the link. I can move data at 50-100MB/s and it cooks along just nice.
What could be going on at link startup? Seems like maybe the transmit from the LX45 is not being locked onto properly by the TUSB9261?
I have a signal trace shown here from chipscope inside the fpga
The TXD is from the fpga to the TUSB
The RXD is from the TUSB back into the fpga - remember in this case the LX45 is the hard disk drive.
My "Reset and Retry" loop seems to work, but I want to make sure I am not missing something else ehre
