SN75DP120 / mainlink output issue

Sho Ogane

Other Parts Discussed in Thread: SN75DP120

Hi all.

I would like to know about SN75DP120.

My customer uses SN75DP120 and connect to PTN3460(eDP to LVDS bridge IC) NXP.
But PTN3460 doesn't recognize mainlink output of SN75DP120.
My customer uses Lane_0 only.
So I have two question.

1. I think SN75DP120 monitor DPCD only, so it doesn't output read data.
    Is my understanding correct?

2. I attach the DPCD register map.
    So please tell me why this device doesn't output mainlink to PTN3460.
    For example, please check 00101h and 00103h register.
    00101h:81→10000001    bit 7=1
    00103h:07→00000111    bit 2=1

    The bit that is not assigned is "1".
    Is it OK?

Fullscreen dpcd_bpm16.txt Download

000000: 11 0A 81 01 00 03 01 81 00 01 00 00 0F 08 00 00 
000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
000020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
000030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 

000080: 09 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
000090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
0000A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
0000B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 

000100: 06 81 00 07 00 00 00 10 00 80 00 00 00 00 00 00 
000110: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
000120: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
000130: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 

000200: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
000210: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00 
000220: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
000230: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 

0003C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
0003D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
0003E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
0003F0: 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 

000500: 00 60 37 33 34 36 30 4E 31 11 01 0A 46 36 00 00 
000510: 00 FF FF FF FF FF FF 00 1A AA 34 12 01 00 00 00 
000520: 01 12 01 03 80 1E 17 78 EA C5 C6 A3 57 4A 9C 23 
000530: 12 4F 54 00 08 00 61 40 01 01 01 01 01 01 01 01 
000540: 01 01 01 01 01 01 64 19 00 40 41 00 26 30 18 88 
000550: 16 00 30 E4 10 00 00 1E 00 00 00 FD 00 37 4B 2A 
000560: 3C 08 00 0A 20 20 20 20 20 20 00 00 00 FC 00 66 
000570: 74 33 5F 78 67 61 30 31 0A 20 20 20 00 00 00 FF 
000580: 00 31 0A 0A 0A 0A 0A 0A 0A 0A 0A 0A 0A 0A 00 B5 
000590: 04 00 03 00 01 00 00 00 01 FE 00 00 08 00 00 0C 
0005A0: 07 FF 1D 0A 14 00 01 02 01 02 00 00 00 00 00 00 
0005B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
0005C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
0005D0: 04 00 00 54 00 C0 00 00 00 00 00 00 00 00 00 00 
0005E0: 00 00 00 00 00 00 00 00 01 02 03 04 05 06 07 08 
0005F0: 09 0A 0B 0C 0D 0E 0F 10 01 78 45 56 12 34 56 78 
000600: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
000610: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
000620: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
000630: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 

000700: 01 85 01 00 00 00 00 00 00 00 00 00 00 00 00 00 
000710: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
000720: 01 02 07 FF 0C 01 10 00 1D 00 00 00 01 FE 00 00 
000730: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

So please tell me advice as soon as possible.

Best Regards,
Sho

over 8 years ago

0 Moises Garcia over 8 years ago

TI__Mastermind 23815 points

Hi Sho Ogane,

You are right, DP120 monitors AUX channel to configure itself, if you don't have AUX channel, it has to ne configured by writing DPCD registers directly.

You need a valid configuration on DPCD registers or DP120 won't enable its outputs.

Writing 0x07 to register 0x00103 is an invalid value, you can see it in DPCD table.

Regards

0 Sho Ogane over 8 years ago in reply to Moises Garcia

Genius 5575 points

Hi Moises san

Thank you for your quick response.

Sorry, I couldn't understand that writing 0x07 to register 0x00103 is an invalid value.
The datasheet is described invalid value the following.
[1:0]/[4:3]: 01/11, 10/10, 10/11, 11/01, 11/10, 11/11
0x07 is [1:0]/[4:3]=11/00, so I think the register value is valid value.

Setting that my customer would like to set is following.
Lane count：one lane
voltage swing：Level 3
Pre-emphasis：default

I think that the following register value is correct.
00101h:01→00000001
00103h:03→00000011

Is it correct?
If it is not, please tell me appropriate register value.

Best Regards,
Sho

0 Moises Garcia over 8 years ago in reply to Sho Ogane

TI__Mastermind 23815 points

Hi Sho-san,

You are right, I was reading wrong the the bit index, bit 2, indicates max swing has been reached. 0x07 is the right value to indicate Vod level 3 is the maximum Vod level.

Once you write the values on DPCD register, can you read them back?

Ar you only writing 0x00101 and 0x00103?
if this is the case could you write 0x00100 and 0x00600 to make sure all registers needed are being configured?

If you are just using one lane with data rate up to 2.7Gbps, have you considered DP119? it just has two lanes and no link training is required.

Regards

0 Sho Ogane over 8 years ago in reply to Moises Garcia

Genius 5575 points

Hi all,

Thank you for your support.

00101h:81→10000001 bit 7=1
00103h:07→00000111 bit 2=1
The bits( 00101h:bit7 and 00103h:bit2) that are not assigned is "1".

I attached register map in first message.
You can see 0x00100 and 0x00600 value.
So please check the register map I attached.

Best Regards,
Sho

0 Moises Garcia over 8 years ago in reply to Sho Ogane

TI__Mastermind 23815 points

Hi Sho-san,

I have seen the register map, I guess that's what you read, the only problem I see from register map is the 0x81 in register 0x00101, it should be 0x01, any value different from 0x01, 0x02 and 0x04 will disable the outputs, could you try setting it to 0x01?

I don't really understand "The bits that are not assigned is "1"."

Regards

Interface

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SN75DP120 / mainlink output issue