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ds90ub940 test pattern initialization sequence / CSI-2 Clock

Goekhan
Prodigy 20 points


Hi,

Can you please send me the initialization sequence for DS90UB940 test pattern generator?

I have the following sequence as listed in 4.3 of AN-2198.

0x66 0x03   # PGCDC = 0x06, set clock divider to 6
0x67 0x06
0x66 0x07   # PGAFS1 = 0x20, set active horizontal width
0x67 0x20
0x66 0x08   # PGAFS2 = 0x03, set active vertical and horizontal width
0x67 0x03
0x66 0x09   # PGAFS3 = 0x1E, set active vertical
0x67 0x1E
0x66 0x04   # PGTFS1 = 0x20, total horizontal width
0x67 0x98
0x66 0x05   # PGTFS2 = 0x20, total horizontal and vertical width
0x67 0xD4
0x66 0x06   # PGTFS3 = 0x20, total vertical width
0x67 0x20
0x66 0x0C   # PGHBP = 0xD8, horizontal back porch
0x67 0xD8
0x66 0x0D   # PGVBP = 0x23, vertical back porch
0x67 0x23
0x65 0x05   # PGCFG Pattern generator creates its own timing / scroll pattern
0x6A 0x22   # 2 Data lines, continuous clock
0x64 0xC5   # PGCTL enable PTG with green test pattern
0x6C 0x13   # CSI Indirect address 0x13
0x6D 0xBF   # CSI Indirect 0x13=0xBF Enable CSI port 0
0x02 0x80   # Enable output


My second question is Datasheet page 40 states that

"The CSI-2 clock frequency is 3.5 times (4 MIPI lanes) or 7
times (2 MIPI lanes) the recovered pixel clock frequency. The MIPI DPHY outputs either 2 or 4 high speed data
lanes (Dn±) according to the CSI-2 protocol. The data rate of each lane is 7 times (4 MIPI lanes) or 14 times (2
MIPI lanes) the pixel clock. As an example in a 4 MIPI lane configuration, at a pixel clock of 150 MHz, the CLK±
runs at 525 MHz, and each data lane runs at 1050 Mbps."

Is this true for both RGB24 and YUV422 8-bit pixel coding?

  • 0
    TI__Genius 14015 points

    Hi Goekhan,

    I'm attaching an example script for configuring the 940 pattern generator for 720p color bar output. Before running this, you should configure the CSI-2 output for the desired mode, which is controlled by 0x6A. None of the output enables in your code need to be done, unless they were already explicitly disabled. The default is that the outputs get enabled automatically when there is video to send - either real video from a serializer or pattern generator mode.

    Fullscreen 940_patgen_720.py Download 
    import time

# Script to setup 940 patgen for 720p

devAddr = 0x58

board.WriteI2C(devAddr, 0x66, 0x00) # (IND) Pattern Generator Red Sub-pixel
time.sleep(0.1)
board.WriteI2C(devAddr, 0x67, 0x00)
time.sleep(0.1)

board.WriteI2C(devAddr, 0x66, 0x01) # (IND) Pattern Generator Green Sub-pixel
time.sleep(0.1)
board.WriteI2C(devAddr, 0x67, 0x00)
time.sleep(0.1)

board.WriteI2C(devAddr, 0x66, 0x02) # (IND) Pattern Generator Blue Sub-pixel
time.sleep(0.1)
board.WriteI2C(devAddr, 0x67, 0x00)
time.sleep(0.1)

board.WriteI2C(devAddr, 0x66, 0x03) # (IND) Pattern Generator Clock Div. Control
time.sleep(0.1)
board.WriteI2C(devAddr, 0x67, 0x03)
time.sleep(0.1)

board.WriteI2C(devAddr, 0x66, 0x04) # (IND) Pattern Generator Total Frame Size 1
time.sleep(0.1)
board.WriteI2C(devAddr, 0x67, 0x72)
time.sleep(0.1)

board.WriteI2C(devAddr, 0x66, 0x05) # (IND) Pattern Generator Total Frame Size 2
time.sleep(0.1)
board.WriteI2C(devAddr, 0x67, 0x26)
time.sleep(0.1)

board.WriteI2C(devAddr, 0x66, 0x06) # (IND) Pattern Generator Total Frame Size 3
time.sleep(0.1)
board.WriteI2C(devAddr, 0x67, 0xee)
time.sleep(0.1)

board.WriteI2C(devAddr, 0x66, 0x07) # (IND) Pattern Generator Active Frame Size 1
time.sleep(0.1)
board.WriteI2C(devAddr, 0x67, 0x00)
time.sleep(0.1)

board.WriteI2C(devAddr, 0x66, 0x08) # (IND) Pattern Generator Active Frame Size 2
time.sleep(0.1)
board.WriteI2C(devAddr, 0x67, 0x25)
time.sleep(0.1)

board.WriteI2C(devAddr, 0x66, 0x09) # (IND) Pattern Generator Active Frame Size 3
time.sleep(0.1)
board.WriteI2C(devAddr, 0x67, 0xd0)
time.sleep(0.1)

board.WriteI2C(devAddr, 0x66, 0x0a) # (IND) Pattern Generator Horizontal Sync Width
time.sleep(0.1)
board.WriteI2C(devAddr, 0x67, 0x28)
time.sleep(0.1)

board.WriteI2C(devAddr, 0x66, 0x0b) # (IND) Pattern Generator Vertical Sync Width
time.sleep(0.1)
board.WriteI2C(devAddr, 0x67, 0x05)
time.sleep(0.1)

board.WriteI2C(devAddr, 0x66, 0x0c) # (IND) Pattern Generator Horizontal Back Porch
time.sleep(0.1)
board.WriteI2C(devAddr, 0x67, 0xdc)
time.sleep(0.1)

board.WriteI2C(devAddr, 0x66, 0x0d) # (IND) Pattern Generator Vertical Back Porch
time.sleep(0.1)
board.WriteI2C(devAddr, 0x67, 0x14)
time.sleep(0.1)

board.WriteI2C(devAddr, 0x65, 0x04) # [2] internal timing source
board.WriteI2C(devAddr, 0x64, 0x05) # [7:4] for pattern sel; [0] enable patgen

    I'm looking into your second question about the MIPI clock rate in YUV mode. I believe the formula from the datasheet holds, but there may be more blanking in between lines since the throughput would go down.

    Thanks,

    Jason

  • 0 in reply to Jason Blackman
    TI__Genius 14015 points
    I confirmed my above statement. When in YUV output mode, the data rate is still 3.5 or 7 times the PCLK.