Description of DP83867IS datasheet

Hi,

I need to answer to my customer.
Please anwser to my questions.

best regards,
g.f.

Hi g.f.

Q1.
Will this ratios will be changed in the next revision datasheet?
Yes, they will be changed to match the DP83867IR datasheet.

Q2.In DP83867IS datasheet page.36, there are followin description:
//////////////////////////////////////////////////////////////////
For SGMII Mode 4 strap, it is recommended to use Rhi=4kΩ and Rlo=10kΩ on
RX_D0 & RX_D1 , RX_D2 & RX_D3.
//////////////////////////////////////////////////////////////////

Is this ratios only recommended for RX_D0 & RX_D1 , RX_D2 & RX_D3 pins
when using SGMII Mode 4 strap?
Yes, when using SGMII, it is suggested to use 4k & 10k resistor values.
If not using SGMII, is Table 6 ratio are recommended for Mode4 strap?
Yes

Q3.
In DP83867IS datasheet page.99 "10.2.1.2" there are recommendation for Clock In(X_I).
I heard that this recommendation is uncorrect and will be removed from DP83867IR datasheet,
and user need to connect clock source directly to X_I whether clock source voltage is 1.8V or 3.3V or 2.5V.
(clock source voltage need to be same as VDDIO voltage)
Is this information also same in DP83867IS?
There was confusion on this point internally. The cap divider is still recommended if the XI source is 2.5V or 3.3V. I will be editing these E2E posts.

Q4.
In DP83867IS datasheet page.8 "8.5 Electrical Characteristics",
minimum high level input voltage(VIH) of 3.3V VDDIO and 2.5 VDDIO are same.
Is this true or typo?
This is true and is not a typo.

Best Regards,

Hi Rob,

I'm very confusing.
I already told my customer to take off the capacitor divider.
If I need to tell them to place capacitor divider again, I want the final answer from TI.

By the way, you told me that X_I and X_O power domain is VDDIO,
so that I thought clock source voltage and VDDIO voltage need to be same voltage.
Are X_I and X_O power domain still VDDIO?

best regards,
g.f.

Hi gf,

My apologies for the confusion. The X_I and X_O power domain is fixed at 1.8V. This is why we recommend the cap divider.

Best Regards,

Hi Rob,

Thank you for the reply.

I understood that X_I and X_O power domain is fixed at 1.8V.
Before telling my customer about recommendation of capacitor divider,
I want to make sure that this is final answer.
Is it final answer and won't be changed in future?

By the way, can I think that capacitor divider are
recommended against all DP83867 device(DP83867IR, DP83867IS, etc)?

best regards,
g.f.

Hi Rob,

I have additional question about XI,XO power domain and clock divider.

Q1.
As you said that XI and XO voltage are fixed to 1.8V,
who are generating this 1.8V?
In following E2E, TI engineer said 1.8V supply is generated from the 2.5V analog supply.
Is it true?
e2e.ti.com/.../1870684

Q2.
I want to know Electrical Characteristics of XI.
What is the value of minimum VIH(High level input voltage)?

Q3.
In latest DP83867IR datasheet page.114 "9.2.1.2 Clock In(XI) Recommendation",
recommended capacitors value for C1 and C2 are same.
In this case, if clock source is 2.5V, the signal amplitude will be 1.25V by capacitor divider.
It is lower than XI voltage(1.8V).
Doesn't it need to adjust  the 2.5V signal amplitude to be 1.8V?

best regards,
g.f.