Hello,
I am using the DP83822 device and controlling its power state through the INT/PWDN_N pin.
I just would like to clarify the BMCR[11] register bit operation. As per the DP83822 datasheet
Power Down:
1 = IEEE Power Down
0 = Normal Operation
The PHY is powered down after this bit is set. Only register access is
enabled during this power down condition. To control the power down
mechanism, this bit is OR'ed with the input from the INT/PWDN_N
pin. When the active low INT/PWDN_N is asserted, this bit is set.
My reading (assuming INT/PWDN_N is programmed to operate as a power down input):
- if PWDN_N is asserted, the device is in power down, the BMCR[11] bit is set.
- In that state,writing a 0 to BMCR[11] has no effect and the part stays in low power state; in other words PWDN_N pin has priority over BMCR[11]. Is that correct ?.
- If PWDN_N is de-asseerted, the device power state is controlled by BMCR[11] state (and other register, but that is anotehr story).
Thanks
Pascal
