Dear All,
I'm trying to connect to TUSB7340 IC via PCIe by using Linux (4.9-rc8 mainline).
lspci -v:
root@am57xx-evm:~# lspci -v
00:00.0 PCI bridge: Texas Instruments Device 8888 (rev 01) (prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0, IRQ 404
Memory at 20100000 (32-bit, non-prefetchable) [size=1M]
Memory at 20020000 (32-bit, non-prefetchable) [size=64K]
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+
Capabilities: [70] Express Root Port (Slot-), MSI 00
Capabilities: [100] Advanced Error Reporting
Kernel driver in use: pcieport
lspci: Unable to load libkmod resources: error -12
(rootfs is from TI's Sitara AM5728 SDK)
The TUSB7340 is connected to PCIe0 bus. Also clock is provided from SoC: CLK_PCIE_R_P and CLK_PCIE_R_N (AG15, AH15).
The PCI_REF_CLK = 100 MHz
Also the CTRL_CORE_PHY_POWER_PCIESS1 = 0x4C00C000 (TX, RX enabled, SYSCLK1 = 76 MHz).
Any more hints?
I do have a question regarding this PCIe clock generation. Shall it be always present when PCIe SS1 block is enabled? I would like to observe it on the Oscilloscope.
dra7.dtsi:
pcie1: pcie@51000000 {
compatible = "ti,dra7-pcie";
reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
reg-names = "rc_dbics", "ti_conf", "config";
interrupts = <0 232 0x4>, <0 233 0x4>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x81000000 0 0 0x03000 0 0x00010000
0x82000000 0 0x20013000 0x13000 0 0xffed000>;
#interrupt-cells = <1>;
num-lanes = <1>;
linux,pci-domain = <0>;
ti,hwmods = "pcie1";
phys = <&pcie1_phy>;
phy-names = "pcie-phy0";
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie1_intc 1>,
<0 0 0 2 &pcie1_intc 2>,
<0 0 0 3 &pcie1_intc 3>,
<0 0 0 4 &pcie1_intc 4>;
pcie1_intc: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
(it is enabled in the "last" dts file).
