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LMH1983: Failed output of 148.35MHz after power up

user4846778
Prodigy 70 points
Part Number: LMH1983

Occasionally, the output of 148.35MHz port (Pin 23 & 24) fails after power up, by channce of around 3/20. The waveform measured then looks wierd as below snapshot (P/N). However, the 148.5MHz port always works fine.

Currently, there is no any configuration for LMH1983. It always boots up with default values, expecting to lock to the input reference (F/V/H and they could be all tied to low or some non-supported format) and generate apporpriate 148.5MHz clock and 148.35MHz clock. What could be the reason for this? And should I have to configure some registers to recover it?


The below snapshots are good 148.35MHz, bad 148.35MHz of P port, bad 148.35MHz of N port. Thank you.

  • 0
    TI__Guru* 93670 points

    Greetings,

    Please let me know:

    1). Does this happen just on power up ? Does it end after sometimes? Or it is continuous for ever until you power down and up?

    2). Could you please let us know what is the alignment mode for PLL3(reg 0x13[5:4])?

    Regards,,nasser

  • 0 in reply to Nasser Mohammadi
    Prodigy 70 points

    Hi Nasser,

    Thank you for the quick reply.

    This problem is continous unless I power down and up again. And it can't disappear even though the external reference alters like between 1080i/50 and 1080i/59. But if it is good after power up, it never becomes bad.

    Currently, there is no host to access the chip, therefore I can't write or read the I2C registers value. I guess the register "TOF3_Align_Mode" should be the default value "11= never align". Anyway, I could try it later to read and write the register values. Is there any suggestion about the register values I should check?

    BTW, the below shapshot is the P&N ports of 148.35MHz clock at a time.

    Thanks again.

  • 0 in reply to user4846778
    TI__Guru* 93670 points
    Thanks for the reply.

    How about if you don't alter the reference signal between 1080i50 and 1080i59? Leave the reference signal at 1080i50 or 1080i59 right from the beginning(i.e when you power up the device)?

    Based on your description a counter is getting reseted. I think if you leave the reference signal as noted above you may not see this. Please check and let us know.

    Regards,,nasser
  • 0 in reply to Nasser Mohammadi
    Prodigy 70 points
    Hi Nasser,
    I tried to tie F/V/H to ground, or give it to a constant format like 1080i/50, but this problem still happens. I just wish to reset the chip by swapping the input format between 1080i/50 and 1080i/59 but it seems no help.
    What "counter" do you mean?
    Thank you.
  • 0 in reply to user4846778
    Prodigy 70 points

    HI Nasser,

    I noticed in the datasheet, it states

    8.3.11.1 TOF3 Initialization Set Up
    Under some circumstances, it is possible for an LMH1983 to power up in an anomalous state in which the output
    of PLL3 exhibits a large amount of cycle-to-cycle jitter. A simple register write after power up will prevent the
    device from remaining in this state. Writing to Register 0x13[5:4] = 10'b to force Always Align Mode ensures that
    the device will not exhibit poor duty cycle performance on CLKout3.

    I added an I2C host and configure this register with value "10b". It could recover the bad output and makes the chip work appropriately. Therefore, I think I have to add this host although it is a bit annoying. It should be much greater if the LMH1983 could be improved on this site in future, because actually I don't need any other configuration for this chip.

    Thank you for the help.

  • 0 in reply to user4846778
    TI__Guru* 93670 points
    Greetings,

    Thanks for the update. I got fixated on the fact you are switching between 50 and 59 frame. This will be noted when we do a new revision of LMH1983.

    Regards,,nasser