High Speed Interface Forum

Hi Tom,

LMH0346 loop bandwidth for HD is 1.5MHz. LMH0346 is going track and pass through jitter with less than 1.5MHz frequency. Therefore 10Hz jitter is going to be tracked and will pass through the device. The device connected at the output of the LMH0346 should be able to track and operate error free. 

Given alignment jitter is within the spec., this tells us there is mainly low frequency jitter. Any idea what is the source of this low frequency jitter? Knowing the root cause of this low frequency jitter can help us to eliminate or attenuate this jitter.

Regards,,nasser

Nasser,

Sir, you did not address my question.

In the LMH0364 DS, the Serial Input Jitter Tolerance for 1483 or 1485 Mbps is >6 UI.

Note 4: Says "Refer to "A1" of SMPTE RP 184-1996.

I believe this is the low frequency jitter spec.

The Serial Output Jitter tolerance for those data rates is < 0.04 UI according to the DS.

What this tells me is that if I inject a signal with less than 6 UI the IC should correct it to <0.04 UI.

Is this correct or not?

If it is correct, than why is it not correcting a 2 UI signal?

I know where the 10 Hz jitter is coming from and I am attempting to correct it.

However, this is a system which drives long cable runs. There is always a degradation in long runs even with SDI receivers that attempt to re-build the signal. So the capability of your re-clocker directly effects our system performance.

This is why we are asking this question.

Regards,

TGM

Hi Tom,

Serial data output jitter of 0.04UI is under the condition of having 24ps(~0.035UI) of input jitter(Please note#7 of the data sheet.). Under this condition, we have maximum 0.04UI of jitter. In other words, this is referring to the intrinsic jitter of the device. With a clean signal - 24ps of jitter - we have maximum 0.04UI of jitter.

Regards,,nasser

Nasser,

A little confusing. However, I see what you are saying. Should there be some improvement with a <6 UI A1 input?

We are seeing none.

Regards,

TGM

Hi Tom,

There is not going to be attenuation or improvement of the jitter since this is within the loop bandwidth of the PLL.

Regards,,nasser

Nasser,

My understanding of PLLs is if the signal is with-in the PLL bandwidth it will get corrected. It will not if it is outside the PLL BW.

We have a camera module with parallel video out being fed to a SDI SERD IC, a GENNUM IC, which is outputting HD-SDI or 3G-SDI with high 10Hz Jitter 8-9 UI. What devices can TI offer to clean up the pixel clock?

Regards,

Tom M.

Hi Tom,

It would be a good idea to check with Gennum to see why this device is putting out high low frequency jitter. I am suspicious perhaps this could be related to Gennum device transmit clock. One idea is to look at a jitter cleaner to clean up the jitter on the transmit clock of this Gennum device(given this is the root cause). Please take a look at TI CDCE62002 jitter cleaner. This could help to clean up jitter being fed into this Gennum device. Maybe you can get evaluation board of this part so you can check this out before you spend your resources on this.

Regards,,nasser