I'd like to understand if DS125BR800A output buffer is a standalone 12.5Gbps driver or a linear amplifier? Essentially to confirm if this is a fully Linear device or not. I believe it is, but wanted to be sure. Thankyou.
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
I'd like to understand if DS125BR800A output buffer is a standalone 12.5Gbps driver or a linear amplifier? Essentially to confirm if this is a fully Linear device or not. I believe it is, but wanted to be sure. Thankyou.
The DS125BR800A is an output capable of driving 12.5 Gbps signals. The output can be configured to have "non-limiting" output voltage characteristics. By "non-limiting" I mean that the input signal amplitude will have an influence on the output voltage amplitude. It would be a stretch to call it "linear" since the input equalizer can support relatively high levels of gain. These high gain levels can result in some non-linear output responses since the maximum output voltage is only ~ 1.2V.
The DS125BR820 has a more "linear" design. The input equalization gain is lower, but the overall result offers improved transparency to input signals with Tx FIR energy.
Regards,
Lee
Hi Lee,
PCIe x1 can link at Pcie Gen3 stable in the pin mode,but unstable in SMBus mode use the same configuation.
PS: I only set 0x06,0x0e,0x0f,0x10 and 0x11.
For SMBus mode the equivalent register settings are different. In the examples below I am using CH0.
To set Tx EQ = Level 4 the register value is 0x0F = 03'h
To set Tx DEM = Level 7 the register values are 0x10 = AC'h and 0x11 = 00'h
To set Rx DEM = Level 9 the register values are 0x10 = AC'h and 0x11 = 04'h
To set Rx EQ = Level 2 the register value is 0x0F = 01'h
Other notes:
Register 0x0E should be 00'h (no need to write 01'h)
Setting 0x0F = 08'h is not included in the CTLE table.
Most PCIe applications keep DEM levels at or below -3.5 dB (values -3.5, -1.5, or 0)
Most PCIe applications keep EQ levels at or below 9.3 dB @ 4 GHz (reg values 00'h, 01'h, 02'h, or 03'h)
Regards,
Lee
Hi Lee,
I am so sorry for mistake.
1. Set TX EQ=Level 4 and TX DEM=Level 7 in pin mode, Set RX EQ=Level 2 and RX DEM= Level 9 in pin mode, It can work in Gen3 stable.
2. Set TX EQ=Level 4 and TX DEM=Level 7 in pin mode; Set RX 0x06=18, 0x0e=08, 0x0f=01, 0x10=ac, 0x11=e4, it work unstable. But change 0x11=e0 or e1, It can work in Gen3 stable.
I just care why there are difference from pin mode and slave mode.
I will try master mode later.