DP83867IR: DP83867 RGMII clock delay

Hi Bennie,

Can you clarify what you mean by "the RX and TX clocks are now zero"?

Does this mean the delay between RX_CLK and RX_D are 0?

Best Regards,

Bennie,

Can you dump the regsiters when in that mode? Specifically I'd like to see register addresses 0x0 to 0x1f, 0x32, & 0x86

Thanks,

Rob:

Thanks for the response.

I will be back to work on Tuesday.

I will re-capture the MDIO data from the Marvel PLC device with the computer set to 100 MHz only, then cut the MDIO/MDC lines and use the emulator to re-create the setup, and then record the registers.

Thanks

Bennie 

Hello:

I monitored the MDIO registers as requested and discovered some issues.

1)  Not all registers in the SNLS484C document match as advertised

-  For instance the clock strapping values appear off.

-  Table 17 and 18 have the same name on the table.

-  Some of the default values do not match the read from power up.

2)  The TX clock delay bit in register 0x0032 is not set (we get 0x00D1 instead of 0x00D3).

-  This matches my symptoms.

-  The Marvell 88LX3142 is in boot mode, so we have not control over it until our software is loaded.

-  Is there any way to strap the TX clock delay enable?  (The RGMII is enabled, and the RX clock delay is enabled).

I have added my characterizing document below.

Thanks
Bennie

Characterizing DP83867 Ethernet PHY Results

By Bennie Kirk, 5-D Systems, Inc.

4 January 2017

 

 

I performed a characterization on the TI D83867 Ethernet PHY due to issues establishing communications between this board and the computer. Figure 1 contains the schematic diagram of the design.

Figure 1 Schematic Diagram with TI DP83867 Ethernet PHY and Marvell 88LX3142 MAC

Initially the circuit would not work with R11 installed, so it is not installed on the following tests. I have not reverted and trouble-shot this issue yet.

My initial theory is the RGMII clock delays were getting reset after initialization, so I recorded the MDIO commands and register values after power up, and after manually entering 88LX3142 commands.

The 88LX3142 commands are:

Read register 0x04:                          0x01E1 

Write register 0x04:                         0x0141

Read register 0x09:                          0x0300

Write register 0x09:                         0x0000

Read register 0x00:                          0x1140

Write register 0x00:                         0x1310

Read register 0x01:                          0x7949

(Repeat reading register 0x01 until it changes)

Read register 0x01:                          0x7969

Read register 0x05:                          0xCDE1

 

Register	Name	Initial Value	After 88LX3142 Command Value	Notes
0x0000	Basic Mode Control	0x1140	0x1100	Strapping change
0x0001	Basic Mode Status	0x796D	0x796D
0x0002	PHY ID 1	0x2000	0x2000
0x0003	PHY ID 2	0xA231	0xA231
0x0004	Auto-Neg Advertise	0x01E1	0x0141	Strapping change
0x0005	Auto-Neg Line Partner	0xCDE1	0xCDE1	Does not match default
0x0006	Auto-Neg Expansion	0x006F	0x006F
0x0007	Auto-Neg Next Page TX	0x2001	0x2001	Table 17 and 18 have the same name (ANNPTR)
0x0008	Auto-Neg Next Page RX	0x4005	0x4005	Does not match default
0x0009	Config Reg 1	0x0300	0x0000	MAC changes this register
0x000A	Status Reg 1	0x7800	0x0800
0x000D	Reg Control	0x0000	0x0000
0x000E	Address/Data	0x0000	0x0000
0x000F	1000 BASE T Status	0x3000	0x3000
0x0010	PHY Control	0x5048	0x5048
0x0011	PHY Status	0x0C02	0x7C02	Status changed?
0x0012	MII IRQ Control	0x0000	0x0000
0x0013	IRQ Status	0x1C40	0x1C40	Does not match default
0x0014	Config Reg 2	0x29C7	0x29C7	Does not match default
0x0015	RX Error Count	0x0000	0x0000
0x0016	BIST Control	0x0000	0x0000
0x0017	Status Reg 2	0x0040	0x0040
0x0018	LED Config 1	0x6150	0x6150
0x0019	LED Config 2	0x4444	0x4444
0x001A	LED Config 3	0x0002	0x0002
0x001E	Config Reg 3	0x0002	0x0002
0x001F	Control Reg	0x0000	0x0000
0x0025	Test Mode Control	0x0400	0x0400
0x0031	Config Reg 4	0x10B0	0x10B0	Does not match default
0x0032	RGMII Control 1	0x00D1	0x00D1	TX Clk not delayed
0x0033	RGMII Control 2	0x0000	0x0000
0x0043	100 BASE TX	0x07A0	0x07A0
0x006E	Strap 1	0x0000	0x0000
0x006F	Strap 2	0x0147	0x0147	Does not match default
0x0071	BIST 1	0x0000	0x0000
0x0072	BIST 2	0x0000	0x0000
0x0086	RGMII Delay	0x00F9	0x00F9	Tx Delay = 4 nSec Rx Delay =2.5 nSec
0x00FE	Loopback	0xE721	0xE721
0x0134	Recv Conf	0x0100	0x0100
0x0135	Recv Stat	0x0000	0x0000

 

Note 1: I have changed several straps during the trouble shooting process:

                LED_0 changed to mode 1 (Open / Open).

                LED_2 changed to mode 1 (Open / Open).

                GPIO_1 changed to mode 3 (11K / 2.49K).

 

Note 2: According to register 0x0086 the clock delays are not getting reset as I initially assumed, but according to register 0x0032 the TX clock delay is not enabled.

 

Note 3: I measured the actual RX clock delay while re-strapping the modes and read the MDIO register 86 after each power up and recorded the following.

 

RX[2] Strap	RX[1] Strap	RX[0] Strap	Register 0x0086	Measured Delay
0	0	0	0x00F7	~2 nSec
0	0	1		(1.5 nSec)
0	1	0	0x00F3	~1 nSec
0	1	1		(0.5 nSec)
1	0	0	0x00FF	~4 nSec
1	0	1		(3.5 nSec)
1	1	0	0x00FD	~3 nSec
1	1	1		(2.5 nSec)

 

I changed the RX[2] and RX[1] strapping to mode 4 and could successfully see data from the computer to the Ethernet Phy, to the 88LX3142 MAC (~3 nSec clock delay). I could see data from the MAC to the Phy with 0 nSec clock delay, but could not receive data from the phy to the computer.

 

Conclusion:

The TX delay is not enabled in register 0x0032 which matches the symptoms noted. We need to figure out how to strap this bit enabled.

 

Hello:

I completed the evaluation of the DP83867 with RESETn held low for >100 mSec after power up and discovered the MDIO register 0x0032 = 0x00D0.

This means that both the RX and TX clock delays are disabled after this power up sequence.

As noted yesterday, power up with RESETn pulled up results in the MDIO register 0x0032 = 0x00D1, and the strapping table (Table 9) does not match the actual values.

I have no control of the Marvell 88LX3142 MAC device during the very first power up boot cycle, and therefore loose communications without a TX clock delay.

I can debug a buffer to get past the boot and remove it afterwards, but I would like to know if there are any UN-advertised straps to overcome this issue?

Thanks

Bennie

Hi Bennie,

It seems like you are having a problem with the strapping of the RGMII CLOCK SKEW TX[2] bit. This bit is tied to the LED_1 pin which is in mode 4 it appears, pulled up. Can you verify this is the case? If so you may have to change your LED_1 circuit such that you enter mode 1.

Best Regards,

Rob:
Thanks for the response.
I have not removed and Ohm'd out these particular resistors, but I believe LED_1 (Pin 46) has 11K pull up and 2.49K pull down.
I measured the voltage at power up and it measures ~0.5 Volts for 180 mSec on power up.
FYI, I have previously removed the resistors to LED_2 (Pin 45) and it measure 0 Volts on power up.
When I had the Launchpad with USB-2-MDIO connected Register 0x0086 read 0x00Fx which according to the table is a 4.0 nSec TX delay. Register 0x0032 on the other hand had 0x00D1 which indicates the TX delay was disabled.
Thanks
Bennie

Hi Bennie,

The nominal cycle time of the data is 4ns, so the data and clk will be aligned at 4ns. Therefor we disable the delay to align the clock to data when 4ns is selected.

Regards,

Rob:
Those sound like the magic words I am looking for.
The Marvell MAC re-negotiates the link to 100 MHz during boot, so I just picked the largest delay I could.
Who knew?
I will let you know one way or the other.
Thanks
Bennie

Rob:

I finally found the combination of straps that works, thanks for your help.

By the way, can you confirm the RGMII clock delay I measured vs the documented table specifications.

 The table below shows the receive clock skew strapping per the documentation.

I connected the Launchpad with USB-2-MDIO to read register 0x0086 after each strap change, and then I used an oscilloscope to measure the delay between the RX data and RX clock.

RX[2] Strap	RX[1] Strap	RX[0] Strap	Register 0x0086	Documented Skew	Measured Skew
0	0	0	0x00F7	0.5 nSec	~2 nSec
0	0	1		1.0 nSec	(1.5 nSec)
0	1	0	0x00F3	1.5 nSec	~1 nSec
0	1	1		2.0 nSec	(0.5 nSec)
1	0	0	0x00FF	2.5 nSec	Disabled
1	0	1		3.0 nSec	(3.5 nSec)
1	1	0	0x00FD	3.5 nSec	~3 nSec
1	1	1		4.0 nSec	(2.5 nSec)

I could not measure the TX clock delay, but when I used the strapping for 2.5 nSec register 0x0032 changed from 0x00D3 to 0x00D1 (maps to 4 n/Sec)

I also could not find any documentation the states the delay control is disabled when 4 nSec is selected.

Thanks Again.

Bennie Kirk

Bennie,

Your measurements of the delays are correct. There is an error in the table in the DP83867IRPAP datasheet. Our team is working on a revision now.

Best Regards,