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SN65LV1224B: Losing of lock in deserilizer

Naga Kiran
Prodigy 30 points
Part Number: SN65LV1224B

I am working on a project which consists of deserializer  (SN65LV1224B) connected to XIlinx's Artix 7 FPGA.

FPGA provides serialized data, and Deserilizer needs to recover clock from the data and deserilize the data. Reference clock frequency is 10 MHz for the deserilizer (Derived from FPGA PLL), and data speed is 100 Mbps.

I have a clock data recovery pattern(6 ones and 6 zeros) before data is being sent.

I find that deserializer is losing lock frequently. Any suggestions on why lock is being lost?

Please help.

  • 0
    TI__Mastermind 29655 points
    Hi Naga,

    Thanks for your patience as we have been out for the Christmas and New Year holidays.

    To understand this issue better, can you share some more information about how you are initializing the device?

    1. Are you using rapid synchronization with the SYNC1 and SYNC2 signals?

    2. Have you tried using random-lock synchronization by sending a data stream directly to the SN65LV1224B without the SYNC training pattern?

    3. Would you be able to share a schematic so we can see how the SN65LV1224B is connected?

    Thanks,

    Michael
  • 0 in reply to Michael Lu (Santa Clara)
    Prodigy 30 points

    Hi Michael,

    Please find answers below:

    1. We are using rapid synchronization, but not with SYNC1 & SYNC2 signals (the serializer is not used).

    The sync-pattern (six ones & six zeros) is given to deserializer (SN65LV1224B) from FPGA.

    2. We haven’t tried the random-lock synchronization.

    3. The schematic and scope shot are in the attached file.SN65LV1224B_schematic-cro_image.docx