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SN65DSI85-Q1: SN65DSI85 PLL Locking issue

Joe Howard
Intellectual 2970 points
Part Number: SN65DSI85-Q1
Other Parts Discussed in Thread: DS90UB928Q

My customer is using this device to go from an SoC (DSI) to our DS90UB947 (LVDS) serializer and eventually deserialized by the DS90UB928Q. We are having some issues bringing up the bridge and getting the DSI/LVDS bridge to lock onto the DSI CLK. I’ve run through the register settings several times and I am convinced that they are correct. For the power-on sequence in the datasheet, we don’t know how to bring the DSI CLK and Data pins to the LP-11 state, so this may be the source of the issue. Any help would be great!

I plan to connect a Ref clock today and try to generate a pattern.

I've attached the register settings.

Thanks for your help!

-Joe

Fullscreen DSI_LVDS_Bridge_Settings.txt Download 
//=====================================================================
// Filename   : DSI_LVDS_Bridge_Settings.txt
//
//   (C) Copyright 2013 by Texas Instruments Incorporated.
//   All rights reserved.
//
//=====================================================================
i2cset -y 1 0x2d 0x09 0x00
i2cset -y 1 0x2d 0x0A 0x05
i2cset -y 1 0x2d 0x0B 0x10
i2cset -y 1 0x2d 0x0D 0x00
i2cset -y 1 0x2d 0x10 0x26
i2cset -y 1 0x2d 0x11 0x00
i2cset -y 1 0x2d 0x12 0x2c
i2cset -y 1 0x2d 0x13 0x00
i2cset -y 1 0x2d 0x18 0x78
i2cset -y 1 0x2d 0x19 0x00
i2cset -y 1 0x2d 0x1A 0x03
i2cset -y 1 0x2d 0x1B 0x00
i2cset -y 1 0x2d 0x20 0x00
i2cset -y 1 0x2d 0x21 0x05
i2cset -y 1 0x2d 0x22 0x00
i2cset -y 1 0x2d 0x23 0x00
i2cset -y 1 0x2d 0x24 0x00
i2cset -y 1 0x2d 0x25 0x00
i2cset -y 1 0x2d 0x26 0x00
i2cset -y 1 0x2d 0x27 0x00
i2cset -y 1 0x2d 0x28 0x21
i2cset -y 1 0x2d 0x29 0x00
i2cset -y 1 0x2d 0x2A 0x00
i2cset -y 1 0x2d 0x2B 0x00
i2cset -y 1 0x2d 0x2C 0x20
i2cset -y 1 0x2d 0x2D 0x00
i2cset -y 1 0x2d 0x2E 0x00
i2cset -y 1 0x2d 0x2F 0x00
i2cset -y 1 0x2d 0x30 0x06
i2cset -y 1 0x2d 0x31 0x00
i2cset -y 1 0x2d 0x32 0x00
i2cset -y 1 0x2d 0x33 0x00
i2cset -y 1 0x2d 0x34 0x50
i2cset -y 1 0x2d 0x35 0x00
i2cset -y 1 0x2d 0x36 0x00
i2cset -y 1 0x2d 0x37 0x00
i2cset -y 1 0x2d 0x38 0x00
i2cset -y 1 0x2d 0x39 0x00
i2cset -y 1 0x2d 0x3A 0x00
i2cset -y 1 0x2d 0x3B 0x00
i2cset -y 1 0x2d 0x3C 0x00
i2cset -y 1 0x2d 0x3D 0x00
i2cset -y 1 0x2d 0x3E 0x00


The PLL_EN bit and SOFT_RESET bit are not set as they need to be set per the recommended sequence defined in the datasheet

  • 0
    TI__Mastermind 18655 points

    Hello Joe,

    It is required by the MIPI spec for the host to drive DSI outputs to LP11 prior to the transition to the HS mode. The initialization/transition sequence requirement is per the MIPI DPHY (Section 6.11) and DSI (Section 5.7) spec requirements.

    If DSI interface is driven to illegal states/protocol by the host, the DSI85 may get into undesirable states:
    - DSI clock or data termination enable may get "stuck"
    - DSI clock does not get enabled internally correctly

    Unexpected behavior may occur when the EN is asserted(transition from 0 to 1) while DSI CLK = LP00.

    The DSI_CLK/DATA should be provided per the recommended initialization sequence (init seq5, Figure7)

    Regards

  • 0 in reply to Joel Jimenez0
    TI__Intellectual 2970 points
    Thanks for the quick reply!

    In the meantime, would I be able to provide a reference clock and get the pattern generator to work without any DSI signals? Can the REFCLK be divided down to from 100MHz?
  • 0 in reply to Joe Howard
    TI__Mastermind 18655 points
    Hello Joe,

    No, when the external REFCLK is used to output the LVDS clock, the internal PLL will generate the output clock frequency based on the REFCLK_MULTIPLIER.

    As a start point, I would suggest using our DSI Tuner tool to generate the register configuration with the test pattern enabled.

    www.ti.com/.../dsi-tuner

    Regards