TCA9406: Why is it necessary to use TCA9406 as a level shifter between 1.8V and 3.3V?

Hello S.P.Lin,

Trying to select one standard design for I2C level shifting can be somewhat challenging due to the fact that each I2C network could have different number of slaves, different load capacitance (due to I2C slave count and PCB/Wire bus capacitance), different voltage range for I2C peripheral, and different data rates.

Are you differentiating between translator/level-shifters and buffers? These are very different devices and I think it would be unwise to group them together.

Generally speaking, the TCA9406 is different from a discrete implementation because it has the one-shot that helps the rising edge transition happen faster, thus it supports higher data-rates. This also dissipated less power than what would be needed in a discrete implementation. 

An integrated solution that also has the pull-up resistors integrated will be a much smaller solution that a discrete implementation, meaning it will require less board space which saves money. There are also costs associated with assembly and therefore the great number of components for a discrete implementation will also increase cost.  The great number of parts also adversely affects MTBF, which is a measure of reliability.

Using a discrete implementation of the translator will also have to deal with lot to lot variation with the devices when designing the circuit. The TCA9406 have matched devices internally.  More care has to be done in selecting the FETs because the thresholds might not lend its self to the specific I2C standard and the associated voltage rails for devices.  Not saying it isn’t doable, but rather care needs to be taken, where our part was designed for I2C and has less risks.

I am a bit concerned that you might want to be use a level shifter in applications that might need a buffer. Unbuffered Level Shifter/Translators work when a device pulls down on the bus, a pass element gets turned on and both sides of the Translators get pulled low, which means the device pulling-down is discharging the capacitive load from both side.  Because of this architecture, the max capacitive load defined by the I2C stand (400pF) is a summation of the loading on both sides of the Translation device.  In a buffered solution, such as TCA9517A, the capacitive loads are decoupled and each side does the pull-down for each respective bus capacitance.  Buffered translators are not easily duplicated with discretes.  This is why I am asking the question about if you are trying to lump unbuffered level shifters with buffered level shifters. 

-Francis Houde