• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 33 subscribers
  • Views 725 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Interfacing ADC with DSP or FPGA

Francisco Eduardo Balart Sanchez
Prodigy 30 points

Good day:

            My name is Francisco Eduardo Balart Sánchez and i’m working in a “concept proof” project which involves digital signal processing. The project is in the phase of implementation, therefore I have to research what devices I need for such implementation and how much the “minimum system” would cost. What solution can you propose?

Here is a more detailed description of the project.

I’m trying to implement digital signal processing to an analog RF signal (CATV) with frequency ranges from 5 MHz to 200 MHz, therefore I know I have to implement a ADC then a DSP or FPGA and after a DAC (plus the signal conditioning PLL’s, etc.), but there some things I don’t understand well.

For example since my greatest frequency is 200 MHz (in which I have to recover the carrier) I try to use an ADC with at least more than the double of 200 MHz. I’ve seen some ADC’s which uses undersampling and others not, if the signal content is in al the 5-200 MHz spectrum I have to use a ADC with more or equal than 400 MSPS? Or is there a way to achieve this with undersampling?

After I choose then an ADC then I don’t know the relation of the clock needed to achieve such SPS. What is the relation between the samples per second and the ADC’s clock?

            Finally the DSP or FPGA selection must meet the speed of the ADC (in the I/O bandwidth specification)

            I hope the previous explain a little bit more the scope of the needs in order to help you to propose a solution (minimum system including clock, PLL, VCO, DAC, etc.).

Thanks in advance 

M.S. Francisco Eduardo Balart Sánchez
dkbf73@motorola.com
Ph. +52 (81) 1301-0215

  • 0
    Prodigy 40 points

    CATV is Cable TV, right? Then 200MHz is not the deciding issue.

    The issue is - how much bandwidth do you need to work with at any given time? Are you looking for TV signals with a bandwidth of 6MHz? Would 10MHz do?

    If you don't need to look at the whole bandwidth, processing becomes much simpler (and cheaper). A LO (Local Oscillator like si570) running at 230MHz - 425MHz will get you an IF signal at 225MHz. You can either mix that down lower, or use undersampling (as you mentioned).

    With undersampling, you use an ADC running at (for example) 100MHz.  The signal at 225MHz will act like its at 25MHz. Depending on the bandwidth of your first IF, you can have a wide patch of RF or a narrow one. You then feed that to your FPGA / DSP, to narrow the selection more (or whatever you want to do)

    If and ADC has parallel output, the clock speed is usually sample speed. If it has a serial output, you get one bit of result per clock, so the sample speed is the clock DIVIDED by the number of bits in the sample.

    Cheers,

    -- Alan Campbell