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DS110DF111: Writing I2C/SMBus software interface/device-driver for DS1110DF111

Part Number: DS110DF111

Hello e2e Forum, please see question from our customer on:

I’m writing an I2C/SMBus software interface/device-driver for the TI DS110DF111 and the register descriptions in the datasheet are a bit unclear.  I’m looking at the REVISED JUNE 2015 version of the datasheet.  Table 7 describes the control and shared register space, and for the Channel Select Register, 0xFF, it shows the mode as read/write.  It also shows bits 7-5 as having some “lock” control and maybe some LOS status.  Then, later in the text, section 7.5.1.9, this register description says The contents of the channel select register, register 0xff, cannot be read back over the SMBus. Read operations on this register will always yield an invalid result.”  It also says “Always write 0x0 to the four most significant bits of register 0xff.”  

 

So which is it?  Is it a write only register, or is it readable?  Should the upper nibble always be zero or not? 

Thank you very much.

  • Register 0xFF bits [7:5] control the LOCK/ADDR0 pin and LOS/INT pin outputs.  These bits are all R/W

     

    0xFF[7:6]  Controls the LOCK/ADDR0 pin output (pin 16)  (Table below)

    If ADDR0 = 0 or Float as sampled on power-up, the LOCK pin output is

    00’b: Logical OR of Lock Status from CH A and CH B

    01’b: Lock Status from Channel A

    10’b: Lock Status from Channel B

    11’b: Logical AND of Lock Status from CH A and CH B

     

    If ADDR0 = 1 as sampled on power-up, the LOCK pin output is

    00’b: Logical NOR of Lock Status from CH A and CH B

    01’b: NOT Lock Status from Channel A

    10’b: NOT Lock Status from Channel B

    11’b: Logical NAND of Lock Status from CH A and CH B

     

    0xFF[5]  Controls the LOS/INT pin output (pin 13)  (Table below)

    If 0xFF[5] = 0'b, then the LOS/INT pin is defined as LOS (loss of signal)

    If 0xFF[5] = 1'b, then the LOS/INT pin is defined as INT (interrupt)

    Regards,

    Lee