Part Number: DP83867CS
Hello,
We're using the DP83867CS in SGMII mode.
Please specify when the RXFSTS UCAST_RCVD and BCAST_RCVD bits are set relative to either the reception of the last Ethernet FCS octet on the wire or on the SGMII line, which I expect would be dependent on a particular RX FIFO setting (RX FIFO DEPTH in PHYCR reg).
In the case of SFD_ERR or BAD_CRC being asserted, is the data being received modified or truncated before being sent onto the SGMII RX line? If so, please specify.
Thank you,
Bob
