Hi
I have a design using the TUSB9261 connected to a Xilinx LX45T FPGA.
When sending data FROM the PC, into the TUSB9261, and then into the Xilinx FPGA, I am getting some kind of bit corruption which makes it appear as invalid Sata Primitives/etc on the receive bus inside the LX45
I believe this an electrical/pll/issue specific to the TUSB9261's power rail. What pins are the most sensitive for noise on the +3.3V rail? Is it VDDA ? I am going to try some different power configurations to try to reduce the noise/corruption effect. It only happens on data from the TUSB9261 and into the LX45T. If I run the LX45T directly on a SATA port, then I do not see this effect. That seems to mean that it is not a reciever issue on the LX45 but something causing noise on the TX pins of the TUSB9261
Anyone have any suggestions there?
