Hi,
Backgraound: I'm going to connect the DP83867IS to 10/100/1000 MAC IP within Altera FPGA. The interface is RGMII and auto-negotiation is required.
I'm little bit confused regarding the GTX_CLK input:
At the pin function table it seems like the GTX_CLK should be 125MHz in all speeds mode of operation:
GTX_CLK 29 I, PD RGMII TRANSMIT CLOCK: This continuous clock signal is sourced from the MAC layer to the PHY. Nominal frequency is 125 MHz.
But in section 9.4.1.2 abou the RGMII interface it looks like it dependent on speed.
9.4.1.2 Reduced GMII (RGMII)
The Reduced Gigabit Media Independent Interface (RGMII) is designed to reduce the number of pins required to
interconnect the MAC and PHY (12 pins for RGMII relative to 24 pins for GMII). To accomplish this goal, the data
paths and all associated control signals are reduced and are multiplexed. Both rising and trailing edges of the
clock are used. For Gigabit operation the GTX_CLK and RX_CLK clocks are 125 MHz, and for 10 and 100 Mbps
operation the clock frequencies are 2.5 MHz and 25 MHz, respectively.
I'll be gratefull if someone can clarify what is the correct clock that should be supllied to the Phy.
Thanks,
Moshe
