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LMH0341: Using LMH0341 with clock rate DDR/2

Part Number: LMH0341

Hi,


I'm using a LMH0341 with an Artix-7 FPGA xc7a35tfgg484-1. The aim is to desereliaze the LVDS signals from LMH, send it to a HD SDI decoder, and send it on HDMI port. With the default configuration of LMH, my design works approximately. By this, I mean that it does not work at every temperature, because the design doest not meet timing once the correct clocking and input/output delay constraints set.


I decided to divide the clock rate of the LMH by setting it in the 28h register. By reading the datasheet, I'm not sure if the LMH keeps transferring data in DDR mode or in SDR mode, and I can't make it work in any SerDes configuration (SelectIO IP in the FPGA in SDR or DDR mode). I can't find any other details about data transfers and timing if the clock rate is divided.


Does anyone have already used the LMH in this clock rate configuration with a FPGA ? It seems that my decode IP doesn't work in that case. I'm using the decoder part of an XAPP Xilinx which you can found here :
www.xilinx.com/.../xapp514.pdf

On page 221, there is a link for the IP


Thanks in advance,

Adrien

  • Hi Adrien,

    LMH0341 has not been used or tested in this clock configuration you noted. LMH0341 was validated and is used by other customers with normal clock rate. I think the best approach is to take care of the timing requirement.

    Regards,,nasser

  • Hi


    Thanks for your answer. After a better analysis of our project, we noticed that the LMH delay constraints could not fit in an Artix 7 speedgrade -1 design, by referring to the DS 181 : Artix7 DC and AC Switching Characteristics document.

    According to this document the speedgrade -2 has a data capture window sufficient to be used with the LMH. Yet, in my design, we're awfully close to the limit, and it doesn't fit in terms of timing requirements, but only with a 10-20ps error. I used the Xilinx forums to have answers and there is no more improvement to make in my design.


    The only way would be to use the LMH clock rate DDR/2 mode, that's why I'd really appreciate to have some answers on it. I cannot make it work with enough Setup and Hold slack in other way..

    Is there any information somewhere, at least with more details than the datasheet ?


    Thanks in advance,

    Adrien

  • Hi Adrien,

    Since we have not characterized/tested the device in this configuration - DDR/2 - we cannot guarantee this operation. We should closely follow figure 3 of the data sheet timing.

    One thought crossed my mind, can you control TX clock ppm tolerance? Can you slow this down to give you more margin on the LMH0341 side?

    Regards,,nasser