Hi,
I'm using a LMH0341 with an Artix-7 FPGA xc7a35tfgg484-1. The aim is to desereliaze the LVDS signals from LMH, send it to a HD SDI decoder, and send it on HDMI port. With the default configuration of LMH, my design works approximately. By this, I mean that it does not work at every temperature, because the design doest not meet timing once the correct clocking and input/output delay constraints set.
I decided to divide the clock rate of the LMH by setting it in the 28h register. By reading the datasheet, I'm not sure if the LMH keeps transferring data in DDR mode or in SDR mode, and I can't make it work in any SerDes configuration (SelectIO IP in the FPGA in SDR or DDR mode). I can't find any other details about data transfers and timing if the clock rate is divided.
Does anyone have already used the LMH in this clock rate configuration with a FPGA ? It seems that my decode IP doesn't work in that case. I'm using the decoder part of an XAPP Xilinx which you can found here :
www.xilinx.com/.../xapp514.pdf
On page 221, there is a link for the IP
Thanks in advance,
Adrien