Hello,
for the design of the ULPI counterpart interface in an ASIC we need ULPI clock jitter specifications (pk-pk jitter). In the datasheet only input requirements are given (600ps RMS jitter). This does not account for the amount of jitter which is added on top of this by the internal PLL for the generation of the ULPI output clock.
Do you have figures therefore?
Kind regards,
Dr. Hannes Muhr, Siemens AG Austria
