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DP83865: MDIO issue

Part Number: DP83865

Hello,

I built 5 proto-type PWAs using DP83865DVH.

I’m working on debugging of this PWA, and facing the following symptom.

I need your help to proceed with debugging.

 

Symptom:

DP83865 does not respond to the MDIO access from the MAC.

See the attached MDIO access. All PWA has the same symptom.

IPC_debug.pdf
 

I tried to apply inverted MDC clock to the PHY, however the same symptom resulted.

 

Question:

What are the conditions does PHY have, to respond to MDIO access?

What are your suggestions/recommendations to proceed with DP83865 MDIO debugging?

 

What do you think?

Thank you.

Regards,

Nakazawa

  • Hi Nakazawa,

    A few things to check here with your issue. First you should check that the PHY does not respond to other PHY addresses in the case that the strap resistor is not being detected properly due to external causes.

    Second, looking at your timing, it appears that MDC is toggling as soon as RESET line is released. Please see section 6.2 in the DP83865 datasheet, specifically time T3.

    T3 shows that MDC should not toggle until 20ms after RESET is released, and during this time, MDIO line should remain high.

    Best Regards,
  • Hello, Rob.

    Thank you for your suggestions for MDIO debugging.

     

    I confirmed your points below.

    First:

    I confirmed that there are no response from the PHY MDIO by changing PHY address 1 to 31 with the PWA#2 and #3.

     

    Second:

    I confirmed MDC toggling timing after RESET release. There is a delay of 20 ms or more before toggling. See the attached.

    I’m using Altera’s IP core MAC that supports DP83865 in my FPGA design. I do not have any user logic on MDC line, just only direct connection with the PHY. There is a bi-directional and Hi-Z logic design on MDIO line.

    mdc_toggling.pdf

    Please let me know if there are other conditions that cause PHY does not respond.

     

    Thank you.

    Nakazawa

  • Hi Nakazawa,

    Please go through this troubleshooting guide to make sure ALL points in the guide are checked and satisfied: www.ti.com/.../snla065a.pdf

    If the PHY is operational and VDDIO is set to the same level(3.3V) as the MDIO interface from the MAC, there should be no problem communicating with the MDIO.

    From your documents, I can not determine which register you are trying to write to. Please use register address 0x0002 and the response will always be 0x2000 if the PHY is brought up properly.

    Please also share a schematic for the PHY portion.

    Best Regards,
  • Hello, Rob.

     

    I attached clock waveform that I measured using active probe.

     clock.pdf

    I could not go through the troubleshooting guide completely, since the MDIO does not work.

    I used to try to issue read/write command to 0x00 BMCR. I captured the waveform at that time.

     

    Can I have email contact info so that I can send my schematics directly?

    I’ll also ask our local supplier if they can send schematics directly to TI.

     

    Thank you.

    Regards,

    Nakazawa

  • Hello Nakazawa,

    I have sent you a connect request along with my email id. You can forward me the schematics offline and we can review it.

    -Regards,
    Aniruddha
  • Hello, Aniruddha.
    I've just sent the schematics for your review.
    Thank you.
    Regards,
    Nakazawa
  • Hello,

    Does anyone who is in TI can reply the schematics review results to me?

    Thank you.

    Regards,

    Nakazawa

  • Nakazawa,

    We are looking into this. We will respond shortly.

    Thank you for your patience,
    -Sam