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TUSB2046B: TUSB2046B Reset Condition

A.Sakai
Prodigy 120 points
Part Number: TUSB2046B
Other Parts Discussed in Thread: TUSB3410

I'd like to ask about TUSB2046B reset condition. TUSB2046B datasheet says followings.

"Generally, a reset with a pulse width between 100 μs and 1 ms is recommended after 3.3-V VCC reaches its 90%. Clock signal has to be active during the last 60 μs of the reset window."

And, SLLA314 Says followings,

"Texas Instruments recommends a minimum of 100 µs to a maximum of 1 ms of reset timing. If the hub is held in reset for a longer period of time, it can fail to respond promptly to USB host signaling and not complete enumeration. This is typically an issue with embedded system applications."

It seems that the reset window is decided for stable enumeration.

My question is,  If we can control external 1.5kohm pull-up register on DP,  is it possible to extend the time of reset window?

Is following sequence acceptable?

  • 0
    TI__Mastermind 18655 points

    Hello Sakai, 

    Sorry, I cannot see your attachemt. You have to implement the below power-up sequence. Could you elaborate on the control of the pull-up on DP?

    Regards

  • 0 in reply to Joel Jimenez0
    Prodigy 120 points

    Hello Joel,

    Thank you for your reply.

    If it is possible to delay the low to high timing of reset , we think we'll control the1.5kohm  pull up resister on DP like attached jpg.

    The pull up resister on DP will be enabled at the same time as asserting reset with transistor.

    We are going to use TUSB2046B with TUSB3410, so we'd like to control the reset of TUSB2046B and TUSB3410 at one time from system MPU  for saving the MPU GPIO resource.

    Best regards,

    Akira Sakai