SN65HVD72: Schematic explanation

Hi Rohit,

This circuit basically makes it so the RS-485 transceiver has two states:

- D signal low: driver is active and drives a negative differential voltage onto the bus (to be interpreted as a logic "low" level by an RS-485 receiver).
- D signal high: driver is inactive (high impedance) and does not drive the bus.

In the second state, the intention is for the undriven bus to be interpreted by a receiver as a logic high level. This can be accomplished by adding external resistors that add a weak positive differential bias to the bus (i.e., pull-up resistor on the A line and pull-down resistor on the B line). This could also be accomplished by using exclusively receivers that feature internal failsafe biasing (like the SN65HVD72). This feature offsets the receiver input thresholds in the negative direction, ensuring that a 0-V differential input is reliably interpreted as a "high" level.

Note that while this scheme can work, it won't benefit from the large noise margin present in standard RS-485 links (in which the high and low states are both actively driven by the transceiver). If you want to retain this margin without adding a separate control line for the DE/RE enable inputs, then you can use a simple timer circuit to generate an enable pulse when the D pin toggles. For an example of this, please see the following reference design:

www.ti.com/.../TIDA-01090

The R/C components used in the 555 timer circuit can then be scaled based on the frame length and data rate required by the application.

I hope this helps; please let me know if you have any other questions.

Best regards,
Max

Rohit,

This would still be bi-directional/half-duplex; you would just need to be sure to keep the D line high when you want to receive data. (In this condition, the /RE and DE pins are low and data from the bus will be reflected on the R output pin.)

Max