With TX_CLK Phase Shift Register 0x0042 (TXCPSR) we can shift the TX_CLK in relation to the Xi clock by 4x the value of bits 0:3 in ns. But what is the basic phase shift when bits 0:3 are 0000? There is no respective spec in the DP83822 datasheet and a bench test with one prototype revealed an initial delay of 10-14ns. Can you specify any valid range or max. delay for DP83822?
-
Ask a related question
What is a related question?A related question is a question created from another question. When the related question is created, it will be automatically linked to the original question.