DS125DF1610: Lock problem

massimo ronchi

Part Number: DS125DF1610
Other Parts Discussed in Thread: DS125MB203, , DS100MB203

I all,
I'm in trouble with the DS125DF1610 device, this device is part of a complex design in which is also present a DS125MB203 chip.

I'm trying to configure del following loopback path toward an onboard FPGA:

FPGA (PRBS source) -> (3inch) -> DS100MB203 -> (7inch) -> (CH0 A RX) DS125DF1610 ->(CH0 A TX)DS125DF1610 -> (7inch) -> DS100MB203 -> (3inch) -> FPGA (PRBS ck)

The final rate will be 12.5G CPRI, to make the setup easy I tryed a 4.9G CPRI rate, in this conditions I'm able to perform the PRBS check without problem, but I'm not able to see the CDR lock bit 4 in reg 0x78 up. The PRBS don't see any error, instead the DS125DF1610 reports a DFE_EQ_ERROR_NO_LOCK.

I'm not able to overcome this error also changing the adaptation, someone can help me?

If I try the same configuration with an upper rate 9.8 I'm not able to perform any test, and the eye of incoming signal is totaly corrupted (instead at 4.9 seems perfect).

Tests made with the following setup (readback from device):

Shared

REG[0x00] = 0x00
REG[0x01] = 0x71
REG[0x02] = 0x00
REG[0x03] = 0x00
REG[0x04] = 0x01
REG[0x05] = 0x08
REG[0x06] = 0x00
REG[0x07] = 0x00
REG[0x08] = 0x00
REG[0x09] = 0x00
REG[0x0A] = 0x01
REG[0x0B] = 0x40
REG[0x0C] = 0x00
REG[0x0D] = 0x41
REG[0x0E] = 0x01
REG[0x0F] = 0xFF
REG[0x10] = 0xFF
REG[0x11] = 0x00

channel 0

REG[0x00] = 0x00
REG[0x01] = 0x80
REG[0x02] = 0x84
REG[0x03] = 0x00
REG[0x04] = 0x01
REG[0x05] = 0x01
REG[0x06] = 0x01
REG[0x07] = 0x01
REG[0x08] = 0x60
REG[0x09] = 0x20
REG[0x0A] = 0x50
REG[0x0B] = 0x6F
REG[0x0C] = 0x08
REG[0x0D] = 0xB4
REG[0x0E] = 0x93
REG[0x0F] = 0x69
REG[0x10] = 0x3A
REG[0x11] = 0x20
REG[0x12] = 0x60
REG[0x13] = 0x90
REG[0x14] = 0x00
REG[0x15] = 0x10
REG[0x16] = 0x7A
REG[0x17] = 0x25
REG[0x18] = 0x40
REG[0x19] = 0x20
REG[0x1A] = 0xA0
REG[0x1B] = 0x03
REG[0x1C] = 0x90
REG[0x1D] = 0x00
REG[0x1E] = 0x21
REG[0x1F] = 0x55
REG[0x20] = 0x00
REG[0x21] = 0x00
REG[0x22] = 0x00
REG[0x23] = 0x02
REG[0x24] = 0x43
REG[0x25] = 0x00
REG[0x26] = 0x00
REG[0x27] = 0x00
REG[0x28] = 0x00
REG[0x29] = 0x00
REG[0x2A] = 0x00
REG[0x2B] = 0x0F
REG[0x2C] = 0xF2
REG[0x2D] = 0x07
REG[0x2E] = 0x00
REG[0x2F] = 0x86
REG[0x30] = 0x08
REG[0x31] = 0x43
REG[0x32] = 0x11
REG[0x33] = 0x88
REG[0x34] = 0x3F
REG[0x35] = 0x1F
REG[0x36] = 0x30
REG[0x37] = 0x00
REG[0x38] = 0x10
REG[0x39] = 0x00
REG[0x3A] = 0x00
REG[0x3B] = 0x31
REG[0x3C] = 0x25
REG[0x3D] = 0x38
REG[0x3E] = 0x00
REG[0x3F] = 0xC4
REG[0x40] = 0x00
REG[0x41] = 0x01
REG[0x42] = 0x04
REG[0x43] = 0x10
REG[0x44] = 0x40
REG[0x45] = 0x08
REG[0x46] = 0x02
REG[0x47] = 0x80
REG[0x48] = 0x03
REG[0x49] = 0x0C
REG[0x4A] = 0x30
REG[0x4B] = 0x41
REG[0x4C] = 0x50
REG[0x4D] = 0xC0
REG[0x4E] = 0x60
REG[0x4F] = 0x90
REG[0x50] = 0x88
REG[0x51] = 0x82
REG[0x52] = 0xA0
REG[0x53] = 0x46
REG[0x54] = 0x52
REG[0x55] = 0x8C
REG[0x56] = 0xB0
REG[0x57] = 0xC8
REG[0x58] = 0x57
REG[0x59] = 0x5D
REG[0x5A] = 0x69
REG[0x5B] = 0x75
REG[0x5C] = 0xD5
REG[0x5D] = 0x99
REG[0x5E] = 0x96
REG[0x5F] = 0xA5
REG[0x60] = 0xB0
REG[0x61] = 0x02
REG[0x62] = 0xB0
REG[0x63] = 0x02
REG[0x64] = 0xDD
REG[0x65] = 0x00
REG[0x66] = 0x00
REG[0x67] = 0x20
REG[0x68] = 0x00
REG[0x69] = 0x0A
REG[0x6A] = 0x22
REG[0x6B] = 0x20
REG[0x6C] = 0x20
REG[0x6D] = 0x20
REG[0x6E] = 0x00
REG[0x6F] = 0x00
REG[0x70] = 0x03
REG[0x71] = 0x00
REG[0x72] = 0x00
REG[0x73] = 0x00
REG[0x74] = 0x00
REG[0x75] = 0x00
REG[0x76] = 0x22
REG[0x77] = 0x1A
REG[0x78] = 0x20
REG[0x79] = 0x13
REG[0x7A] = 0x00
REG[0x7B] = 0x00
REG[0x7C] = 0x00
REG[0x7D] = 0x44
REG[0x7E] = 0x83
REG[0x7F] = 0x2A
REG[0x80] = 0x00
REG[0x81] = 0x00
REG[0x82] = 0x00
REG[0x83] = 0x00
REG[0x84] = 0x00
REG[0x85] = 0x00
REG[0x86] = 0x20
REG[0x87] = 0xA6
REG[0x88] = 0x0C
REG[0x89] = 0x00
REG[0x8A] = 0x00
REG[0x8B] = 0x00
REG[0x8C] = 0x00
REG[0x8D] = 0x06
REG[0x8E] = 0x1C
REG[0x8F] = 0x00
REG[0x90] = 0x00
REG[0x91] = 0x00
REG[0x92] = 0x00
REG[0x93] = 0x00
REG[0x94] = 0x00
REG[0x95] = 0x00
REG[0x96] = 0x1C
REG[0x97] = 0x00
REG[0x98] = 0xC0
REG[0x99] = 0x3F
REG[0x9A] = 0x3F
REG[0x9B] = 0x00

Thanks
Maxx

over 8 years ago

0 Lee Sledjeski over 8 years ago

TI__Mastermind 43795 points

Hi Maxx,

Please indicate the settings on the MB203 devices as well.

Thanks and Regards,

Lee

0 massimo ronchi over 8 years ago in reply to Lee Sledjeski

Intellectual 320 points

Hi Lee,
Thank you for the fast response I'm in trouble i need to solve this problem before the hardware re-spin.

The test setup is the following
FPGA -> (D_IN0) DS125MB203 (S_OUTB0)-> DS125DF1610 -> (S_INB0) DS125MB203 (D_OUT0)-> FPGA

Reg[0x0] = 00000000
Reg[0x1] = 00000000
Reg[0x2] = 00000001
Reg[0x3] = 00000000
Reg[0x4] = 00000000
Reg[0x5] = 00000000
Reg[0x6] = 00000018
Reg[0x7] = 00000001
Reg[0x8] = 0000000C
Reg[0x9] = 00000000
Reg[0xa] = 00000000
Reg[0xb] = 00000070
Reg[0xc] = 00000000
Reg[0xd] = 00000000
Reg[0xe] = 00000000
Reg[0xf] = 00000000
Reg[0x10] = 000000AD
Reg[0x11] = 00000082
Reg[0x12] = 00000000
Reg[0x13] = 00000000
Reg[0x14] = 00000000
Reg[0x15] = 0000000C
Reg[0x16] = 00000007
Reg[0x17] = 000000ED
Reg[0x18] = 00000080
Reg[0x19] = 00000000
Reg[0x1a] = 00000000
Reg[0x1b] = 00000000
Reg[0x1c] = 00000000
Reg[0x1d] = 00000000
Reg[0x1e] = 000000AD
Reg[0x1f] = 00000082
Reg[0x20] = 00000000
Reg[0x21] = 00000000
Reg[0x22] = 00000000
Reg[0x23] = 00000000
Reg[0x24] = 00000000
Reg[0x25] = 000000AD
Reg[0x26] = 00000080
Reg[0x27] = 00000000
Reg[0x28] = 0000000C
Reg[0x29] = 00000000
Reg[0x2a] = 00000000
Reg[0x2b] = 0000000C
Reg[0x2c] = 00000000
Reg[0x2d] = 000000ED
Reg[0x2e] = 00000080
Reg[0x2f] = 00000000
Reg[0x30] = 00000000
Reg[0x31] = 00000000
Reg[0x32] = 00000000
Reg[0x33] = 0000002F
Reg[0x34] = 000000AD
Reg[0x35] = 00000082
Reg[0x36] = 00000000
Reg[0x37] = 00000000
Reg[0x38] = 00000000
Reg[0x39] = 00000000
Reg[0x3a] = 00000000
Reg[0x3b] = 000000AD
Reg[0x3c] = 00000080
Reg[0x3d] = 00000000
Reg[0x3e] = 00000000
Reg[0x3f] = 00000000
Reg[0x40] = 00000000
Reg[0x41] = 0000002F
Reg[0x42] = 000000AD
Reg[0x43] = 00000082
Reg[0x44] = 00000000
Reg[0x45] = 00000000
Reg[0x46] = 00000038
Reg[0x47] = 00000000
Reg[0x48] = 00000005
Reg[0x49] = 00000000
Reg[0x4a] = 00000000
Reg[0x4b] = 00000000
Reg[0x4c] = 00000000
Reg[0x4d] = 00000000
Reg[0x4e] = 00000000
Reg[0x4f] = 00000000
Reg[0x50] = 00000000
Reg[0x51] = 00000046
Reg[0x52] = 00000000
Reg[0x53] = 00000000
Reg[0x54] = 00000000
Reg[0x55] = 00000000
Reg[0x56] = 00000010
Reg[0x57] = 00000044
Reg[0x58] = 00000020
Reg[0x59] = 00000000
Reg[0x5a] = 00000054
Reg[0x5b] = 00000054
Reg[0x5c] = 00000000
Reg[0x5d] = 00000000
Reg[0x5e] = 00000000
Reg[0x5f] = 00000000

Maxx

0 Lee Sledjeski over 8 years ago in reply to massimo ronchi

TI__Mastermind 43795 points

Hi Maxx,

Here are some more optimized settings for the DS125MB203

You can sustitute these into the current settings.

Reg 0x16 = 00'h \\* min setting SIN_B0

Reg 0x18 = EA'h \\* 800 mV - limiting output style for DOUT_0

Reg 0x33 = 00'h \\* min EQ setting - just to change unused default '2F setting

Reg 0x34 = EA'h \\* 800 mV - limiting output style for SOUT_B0

Reg 0x35 = 00'h \\* 0 dB DEM - for SOUT_B0

See if this cleans up the errors at higher rates.

Regards,

Lee

0 massimo ronchi over 8 years ago in reply to Lee Sledjeski

Intellectual 320 points

Hi Lee,

Nothing good at higher rate ..see the eyes!

Reg[0x0] = 0x00000000

Reg[0x1] = 0x00000000

Reg[0x2] = 0x00000001

Reg[0x3] = 0x00000000

Reg[0x4] = 0x00000000

Reg[0x5] = 0x00000000

Reg[0x6] = 0x00000018

Reg[0x7] = 0x00000001

Reg[0x8] = 0x0000000C

Reg[0x9] = 0x00000000

Reg[0xa] = 0x00000000

Reg[0xb] = 0x00000070

Reg[0xc] = 0x00000000

Reg[0xd] = 0x00000000

Reg[0xe] = 0x00000000

Reg[0xf] = 0x00000000

Reg[0x10] = 0x000000AD

Reg[0x11] = 0x00000082

Reg[0x12] = 0x00000000

Reg[0x13] = 0x00000000

Reg[0x14] = 0x00000000

Reg[0x15] = 0x0000000C

Reg[0x16] = 0x00000000

Reg[0x17] = 0x000000ED

Reg[0x18] = 0x000000EA

Reg[0x19] = 0x00000000

Reg[0x1a] = 0x00000000

Reg[0x1b] = 0x00000000

Reg[0x1c] = 0x00000000

Reg[0x1d] = 0x00000000

Reg[0x1e] = 0x000000AD

Reg[0x1f] = 0x00000082

Reg[0x20] = 0x00000000

Reg[0x21] = 0x00000000

Reg[0x22] = 0x00000000

Reg[0x23] = 0x00000000

Reg[0x24] = 0x00000000

Reg[0x25] = 0x000000AD

Reg[0x26] = 0x00000080

Reg[0x27] = 0x00000000

Reg[0x28] = 0x0000000C

Reg[0x29] = 0x00000000

Reg[0x2a] = 0x00000000

Reg[0x2b] = 0x0000000C

Reg[0x2c] = 0x00000000

Reg[0x2d] = 0x000000ED

Reg[0x2e] = 0x00000080

Reg[0x2f] = 0x00000000

Reg[0x30] = 0x00000000

Reg[0x31] = 0x00000000

Reg[0x32] = 0x00000000

Reg[0x33] = 0x00000000

Reg[0x34] = 0x000000EA

Reg[0x35] = 0x00000080

Reg[0x36] = 0x00000000

Reg[0x37] = 0x00000000

Reg[0x38] = 0x00000000

Reg[0x39] = 0x00000000

Reg[0x3a] = 0x00000000

Reg[0x3b] = 0x000000AD

Reg[0x3c] = 0x00000080

Reg[0x3d] = 0x00000000

Reg[0x3e] = 0x00000000

Reg[0x3f] = 0x00000000

Reg[0x40] = 0x00000000

Reg[0x41] = 0x0000002F

Reg[0x42] = 0x000000AD

Reg[0x43] = 0x00000082

Reg[0x44] = 0x00000000

Reg[0x45] = 0x00000000

Reg[0x46] = 0x00000038

Reg[0x47] = 0x00000000

Reg[0x48] = 0x00000005

Reg[0x49] = 0x00000000

Reg[0x4a] = 0x00000000

Reg[0x4b] = 0x00000000

Reg[0x4c] = 0x00000000

Reg[0x4d] = 0x00000000

Reg[0x4e] = 0x00000000

Reg[0x4f] = 0x00000000

Reg[0x50] = 0x00000000

Reg[0x51] = 0x00000046

Reg[0x52] = 0x00000000

Reg[0x53] = 0x00000000

Reg[0x54] = 0x00000000

Reg[0x55] = 0x00000000

Reg[0x56] = 0x00000010

Reg[0x57] = 0x00000044

Reg[0x58] = 0x00000020

Reg[0x59] = 0x00000000

Reg[0x5a] = 0x00000054

Reg[0x5b] = 0x00000054

Reg[0x5c] = 0x00000000

Reg[0x5d] = 0x00000000

Reg[0x5e] = 0x00000000

Reg[0x5f] = 0x00000000

Maxx

0 massimo ronchi over 8 years ago in reply to massimo ronchi

Intellectual 320 points

Hi Lee,
I have all the bosses breathing on my neck, sorry, do you have some news for me ?

Questions :

a) Do you think that the 7 inch length of our trace on FR4 at 9/12.5G may cause this problem (provided that are made right for RF) or I have to change the PCB dielectric?

b) Loosing some functionality (in PCB re-spin) I can reduce the traces length to 3 inch between the FPGA and the 1610 (unmounting the BR203), do you have successful cases at 12.5G on FR4?

c) Do you think that the unlock problem is related to some problem on chip power rail or reference clock (25Mhz) or due to the error DFE_EQ_ERROR_NO_LOCK there is some un-compatibility between the BR203 and the 1610 chips?

d) We can generate a PRBS without a channel lock ?

If yes, do you have an example to follow ?

e) We can check the PRBS without a channel lock ?
If yes, do you have an example to follow ?

Thanks
Maxx

0 massimo ronchi over 8 years ago in reply to massimo ronchi

Intellectual 320 points

Hi Lee,
I have done other tests and now I'm able to Lock on 4.9G but persist the problems with the 9.8 not able to lock.

Moreover can you confirm that is right your suggestion

Reg 0x18 = EA'h \\* 800 mV - limiting output style for DOUT_0

I suppose Reg 17

TEST WITH 4.9G
BR203

REG[0x0] = 0x00000000
REG[0x1] = 0x00000000
REG[0x2] = 0x00000001
REG[0x3] = 0x00000000
REG[0x4] = 0x00000000
REG[0x5] = 0x00000000
REG[0x6] = 0x00000018
REG[0x7] = 0x00000001
REG[0x8] = 0x0000000C
REG[0x9] = 0x00000000
REG[0xa] = 0x00000000
REG[0xb] = 0x00000070
REG[0xc] = 0x00000000
REG[0xd] = 0x00000000
REG[0xe] = 0x00000000
REG[0xf] = 0x00000000
REG[0x10] = 0x000000AD
REG[0x11] = 0x00000082
REG[0x12] = 0x00000000
REG[0x13] = 0x00000000
REG[0x14] = 0x00000000
REG[0x15] = 0x0000000C
REG[0x16] = 0x00000000
REG[0x17] = 0x000000EA
REG[0x18] = 0x00000080
REG[0x19] = 0x00000000
REG[0x1a] = 0x00000000
REG[0x1b] = 0x00000000
REG[0x1c] = 0x00000000
REG[0x1d] = 0x00000000
REG[0x1e] = 0x000000AD
REG[0x1f] = 0x00000082
REG[0x20] = 0x00000000
REG[0x21] = 0x00000000
REG[0x22] = 0x00000000
REG[0x23] = 0x00000000
REG[0x24] = 0x00000000
REG[0x25] = 0x000000AD
REG[0x26] = 0x00000080
REG[0x27] = 0x00000000
REG[0x28] = 0x0000000C
REG[0x29] = 0x00000000
REG[0x2a] = 0x00000000
REG[0x2b] = 0x0000000C
REG[0x2c] = 0x00000000
REG[0x2d] = 0x000000ED
REG[0x2e] = 0x00000080
REG[0x2f] = 0x00000000
REG[0x30] = 0x00000000
REG[0x31] = 0x00000000
REG[0x32] = 0x00000000
REG[0x33] = 0x00000000
REG[0x34] = 0x000000EA
REG[0x35] = 0x00000080
REG[0x36] = 0x00000000
REG[0x37] = 0x00000000
REG[0x38] = 0x00000000
REG[0x39] = 0x00000000
REG[0x3a] = 0x00000000
REG[0x3b] = 0x000000AD
REG[0x3c] = 0x00000080
REG[0x3d] = 0x00000000
REG[0x3e] = 0x00000000
REG[0x3f] = 0x00000000
REG[0x40] = 0x00000000
REG[0x41] = 0x0000002F
REG[0x42] = 0x000000AD
REG[0x43] = 0x00000082
REG[0x44] = 0x00000000
REG[0x45] = 0x00000000
REG[0x46] = 0x00000038
REG[0x47] = 0x00000000
REG[0x48] = 0x00000005
REG[0x49] = 0x00000000
REG[0x4a] = 0x00000000
REG[0x4b] = 0x00000000
REG[0x4c] = 0x00000000
REG[0x4d] = 0x00000000
REG[0x4e] = 0x00000000
REG[0x4f] = 0x00000000
REG[0x50] = 0x00000000
REG[0x51] = 0x00000046
REG[0x52] = 0x00000000
REG[0x53] = 0x00000000
REG[0x54] = 0x00000000
REG[0x55] = 0x00000000
REG[0x56] = 0x00000010
REG[0x57] = 0x00000044
REG[0x58] = 0x00000020
REG[0x59] = 0x00000000
REG[0x5a] = 0x00000054
REG[0x5b] = 0x00000054
REG[0x5c] = 0x00000000
REG[0x5d] = 0x00000000
REG[0x5e] = 0x00000000
REG[0x5f] = 0x00000000

Shared DF1610

REG[0x00] = 0x00
REG[0x01] = 0x71
REG[0x02] = 0x00
REG[0x03] = 0x00
REG[0x04] = 0x01
REG[0x05] = 0x08
REG[0x06] = 0x00
REG[0x07] = 0x05
REG[0x08] = 0x01
REG[0x09] = 0x00
REG[0x0A] = 0x01
REG[0x0B] = 0x40
REG[0x0C] = 0x00
REG[0x0D] = 0x4D
REG[0x0E] = 0x02
REG[0x0F] = 0xFF
REG[0x10] = 0xFF
REG[0x11] = 0x00

channel = 0

REG[0x00] = 0x00
REG[0x01] = 0x80
REG[0x02] = 0x9C
REG[0x03] = 0x00
REG[0x04] = 0x01
REG[0x05] = 0x01
REG[0x06] = 0x01
REG[0x07] = 0x01
REG[0x08] = 0x60
REG[0x09] = 0x00
REG[0x0A] = 0x00
REG[0x0B] = 0x6F
REG[0x0C] = 0x08
REG[0x0D] = 0xB4
REG[0x0E] = 0x93
REG[0x0F] = 0x69
REG[0x10] = 0x3A
REG[0x11] = 0x20
REG[0x12] = 0xE0
REG[0x13] = 0x90
REG[0x14] = 0x00
REG[0x15] = 0x12
REG[0x16] = 0x7A
REG[0x17] = 0x25
REG[0x18] = 0x40
REG[0x19] = 0x20
REG[0x1A] = 0xA0
REG[0x1B] = 0x03
REG[0x1C] = 0x90
REG[0x1D] = 0x00
REG[0x1E] = 0xE1
REG[0x1F] = 0x55
REG[0x20] = 0x00
REG[0x21] = 0x00
REG[0x22] = 0x00
REG[0x23] = 0x41
REG[0x24] = 0x00
REG[0x25] = 0x00
REG[0x26] = 0x00
REG[0x27] = 0x39
REG[0x28] = 0xA2
REG[0x29] = 0x40
REG[0x2A] = 0x30
REG[0x2B] = 0x0F
REG[0x2C] = 0xF2
REG[0x2D] = 0x04
REG[0x2E] = 0x00
REG[0x2F] = 0x86
REG[0x30] = 0x00
REG[0x31] = 0x40
REG[0x32] = 0x11
REG[0x33] = 0x88
REG[0x34] = 0xBF
REG[0x35] = 0x1F
REG[0x36] = 0x30
REG[0x37] = 0x01
REG[0x38] = 0x10
REG[0x39] = 0x00
REG[0x3A] = 0x00
REG[0x3B] = 0x31
REG[0x3C] = 0x25
REG[0x3D] = 0x3F
REG[0x3E] = 0x40
REG[0x3F] = 0xC0
REG[0x40] = 0x00
REG[0x41] = 0x01
REG[0x42] = 0x04
REG[0x43] = 0x10
REG[0x44] = 0x40
REG[0x45] = 0x08
REG[0x46] = 0x02
REG[0x47] = 0x80
REG[0x48] = 0x03
REG[0x49] = 0x0C
REG[0x4A] = 0x30
REG[0x4B] = 0x41
REG[0x4C] = 0x50
REG[0x4D] = 0xC0
REG[0x4E] = 0x60
REG[0x4F] = 0x90
REG[0x50] = 0x88
REG[0x51] = 0x82
REG[0x52] = 0xA0
REG[0x53] = 0x46
REG[0x54] = 0x52
REG[0x55] = 0x8C
REG[0x56] = 0xB0
REG[0x57] = 0xC8
REG[0x58] = 0x57
REG[0x59] = 0x5D
REG[0x5A] = 0x69
REG[0x5B] = 0x75
REG[0x5C] = 0xD5
REG[0x5D] = 0x99
REG[0x5E] = 0x96
REG[0x5F] = 0xA5
REG[0x60] = 0xB0
REG[0x61] = 0x02
REG[0x62] = 0xB0
REG[0x63] = 0x02
REG[0x64] = 0xDD
REG[0x65] = 0x00
REG[0x66] = 0x00
REG[0x67] = 0x20
REG[0x68] = 0x00
REG[0x69] = 0x0A
REG[0x6A] = 0x22
REG[0x6B] = 0x40
REG[0x6C] = 0x00
REG[0x6D] = 0x00
REG[0x6E] = 0x00
REG[0x6F] = 0x00
REG[0x70] = 0x03
REG[0x71] = 0x21
REG[0x72] = 0x10
REG[0x73] = 0x01
REG[0x74] = 0x10
REG[0x75] = 0x10
REG[0x76] = 0x22
REG[0x77] = 0x1A
REG[0x78] = 0x3C
REG[0x79] = 0x13
REG[0x7A] = 0x00
REG[0x7B] = 0x00
REG[0x7C] = 0x00
REG[0x7D] = 0x48
REG[0x7E] = 0x13
REG[0x7F] = 0x3A
REG[0x80] = 0x39
REG[0x81] = 0xE4
REG[0x82] = 0x00
REG[0x83] = 0x00
REG[0x84] = 0x00
REG[0x85] = 0x00
REG[0x86] = 0x20
REG[0x87] = 0x24
REG[0x88] = 0x0C
REG[0x89] = 0x00
REG[0x8A] = 0x00
REG[0x8B] = 0x00
REG[0x8C] = 0x00
REG[0x8D] = 0x02
REG[0x8E] = 0x1C
REG[0x8F] = 0x01
REG[0x90] = 0x00
REG[0x91] = 0x00
REG[0x92] = 0x00
REG[0x93] = 0x00
REG[0x94] = 0x00
REG[0x95] = 0x00
REG[0x96] = 0x1C
REG[0x97] = 0x00
REG[0x98] = 0x0C
REG[0x99] = 0x3F
REG[0x9A] = 0x3F
REG[0x9B] = 0x00

TEST WITH 9.8G

REG[0x00] = 0x00pChan 0
REG[0x01] = 0x80
REG[0x02] = 0x04
REG[0x03] = 0x00
REG[0x04] = 0x01
REG[0x05] = 0x01
REG[0x06] = 0x01
REG[0x07] = 0x01
REG[0x08] = 0x60
REG[0x09] = 0x00
REG[0x0A] = 0x00
REG[0x0B] = 0x6F
REG[0x0C] = 0x08
REG[0x0D] = 0xB4
REG[0x0E] = 0x93
REG[0x0F] = 0x69
REG[0x10] = 0x3A
REG[0x11] = 0x20
REG[0x12] = 0xE0
REG[0x13] = 0x90
REG[0x14] = 0x00
REG[0x15] = 0x12
REG[0x16] = 0x7A
REG[0x17] = 0x25
REG[0x18] = 0x40
REG[0x19] = 0x20
REG[0x1A] = 0xA0
REG[0x1B] = 0x03
REG[0x1C] = 0x90
REG[0x1D] = 0x00
REG[0x1E] = 0xE1
REG[0x1F] = 0x55
REG[0x20] = 0x00
REG[0x21] = 0x00
REG[0x22] = 0x00
REG[0x23] = 0x41
REG[0x24] = 0x40
REG[0x25] = 0x00
REG[0x26] = 0x00
REG[0x27] = 0x00
REG[0x28] = 0x00
REG[0x29] = 0x00
REG[0x2A] = 0x30
REG[0x2B] = 0x0F
REG[0x2C] = 0xF2
REG[0x2D] = 0x04
REG[0x2E] = 0x00
REG[0x2F] = 0x86
REG[0x30] = 0x00
REG[0x31] = 0x40
REG[0x32] = 0x11
REG[0x33] = 0x88
REG[0x34] = 0xBF
REG[0x35] = 0x1F
REG[0x36] = 0x30
REG[0x37] = 0x00
REG[0x38] = 0x00
REG[0x39] = 0x00
REG[0x3A] = 0x00
REG[0x3B] = 0x30
REG[0x3C] = 0xC1
REG[0x3D] = 0x3F
REG[0x3E] = 0x40
REG[0x3F] = 0xC0
REG[0x40] = 0x00
REG[0x41] = 0x01
REG[0x42] = 0x04
REG[0x43] = 0x10
REG[0x44] = 0x40
REG[0x45] = 0x08
REG[0x46] = 0x02
REG[0x47] = 0x80
REG[0x48] = 0x03
REG[0x49] = 0x0C
REG[0x4A] = 0x30
REG[0x4B] = 0x41
REG[0x4C] = 0x50
REG[0x4D] = 0xC0
REG[0x4E] = 0x60
REG[0x4F] = 0x90
REG[0x50] = 0x88
REG[0x51] = 0x82
REG[0x52] = 0xA0
REG[0x53] = 0x46
REG[0x54] = 0x52
REG[0x55] = 0x8C
REG[0x56] = 0xB0
REG[0x57] = 0xC8
REG[0x58] = 0x57
REG[0x59] = 0x5D
REG[0x5A] = 0x69
REG[0x5B] = 0x75
REG[0x5C] = 0xD5
REG[0x5D] = 0x99
REG[0x5E] = 0x96
REG[0x5F] = 0xA5
REG[0x60] = 0xB0
REG[0x61] = 0x02
REG[0x62] = 0xB0
REG[0x63] = 0x02
REG[0x64] = 0xDD
REG[0x65] = 0x00
REG[0x66] = 0x00
REG[0x67] = 0x20
REG[0x68] = 0x00
REG[0x69] = 0x0A
REG[0x6A] = 0x22
REG[0x6B] = 0x40
REG[0x6C] = 0x00
REG[0x6D] = 0x00
REG[0x6E] = 0x00
REG[0x6F] = 0x00
REG[0x70] = 0x03
REG[0x71] = 0x20
REG[0x72] = 0x00
REG[0x73] = 0x00
REG[0x74] = 0x00
REG[0x75] = 0x00
REG[0x76] = 0x22
REG[0x77] = 0x1A
REG[0x78] = 0x24
REG[0x79] = 0x13
REG[0x7A] = 0x00
REG[0x7B] = 0x00
REG[0x7C] = 0x00
REG[0x7D] = 0x48
REG[0x7E] = 0x13
REG[0x7F] = 0x3A
REG[0x80] = 0x00
REG[0x81] = 0xE4
REG[0x82] = 0x00
REG[0x83] = 0x00
REG[0x84] = 0x00
REG[0x85] = 0x00
REG[0x86] = 0x20
REG[0x87] = 0x24
REG[0x88] = 0x0C
REG[0x89] = 0x00
REG[0x8A] = 0x00
REG[0x8B] = 0x00
REG[0x8C] = 0x00
REG[0x8D] = 0x02
REG[0x8E] = 0x1C
REG[0x8F] = 0x60
REG[0x90] = 0x00
REG[0x91] = 0x00
REG[0x92] = 0x00
REG[0x93] = 0x00
REG[0x94] = 0x00
REG[0x95] = 0x00
REG[0x96] = 0x1C
REG[0x97] = 0x00
REG[0x98] = 0x0C
REG[0x99] = 0x3F
REG[0x9A] = 0x3F
REG[0x9B] = 0x00

Thanks
Maxx

0 Lee Sledjeski over 8 years ago in reply to massimo ronchi

TI__Mastermind 43795 points

Hi Maxx,

Yes, register 0x17 is correct for VOD. Can you post the eye diagrams for 4.9 Gbps?

Thanks and Regards,

Lee

0 massimo ronchi over 8 years ago in reply to Lee Sledjeski

Intellectual 320 points

Hi Lee,
In a previous chat you can find the 9.8G and 4.9 G eyes.
Maxx

0 Lee Sledjeski over 8 years ago in reply to massimo ronchi

TI__Mastermind 43795 points

Please repost so I know I am looking at the correct information.

0 massimo ronchi over 8 years ago in reply to Lee Sledjeski

Intellectual 320 points

Hi Lee,

Here you can find 4G9 eye with and without DFE on FPGA, then I have tried 6G1 without success and the eys is very strange, seems that the retimed data are not at the right frequency (I set the rate REG[2F]=0x96) the last eye is at 9G8.

Thanks Maxx