DS92LV18: Startup condition and cause for unlock

Hi Satoshi,

The reference on page 13 is when the Start/Stop transition is not detected two times in a row.

This could be an indication of poor signal quality. 

#3  The SYNC signal can be asserted at any time. 

#4  The SYNC signal can be asserted at startup.

Regards,

Lee 

Lee-san

Thank you for reply.

About poor signal quality, what cause is poor signal quality?
（For example, line, clock, noise, and the other）
If there way to strong signal, please let me know.

Best regards,
Satoshi

Hi Satoshi-san,

Poor signal quality can occur for many reasons.  Here are a few typical examples.

1. Large Impedance change very close to transmitter pins.

2. Improper termination value or no termination.

3.  Capacitive coupling between differential signal pairs.

4. Power supply problems. 

Can you describe with schematic or picture the DS92LV18 application?

Can you measure the waveform at the DS92LV18 inputs?

Regards,

Lee

Lee-san

Thank you for reply.

Schematic is attached, please see below.

Addition, please let me know about two points below for DS92LV18.

①For measure the waveform, how are determine below spec for 60MHz-customer condition?  

　・tRMNI-Right and tRMHI-Left：About datasheet page-5, are 15MHz condition and 66MHz condition proportional relation?

　・tDJIT+ and tDJIT- ：These specs are not described on the datasheet. I think that these spec can reference tJI spec, is it correct?

②Is there generate PRBS pattern of DS92LV18 ?

 

Best regards,

Satoshi

Satoshi-san,

I would try replacing the ferrite bead in the GND path.  We do not usually see this requirement.

I would replace one of the 0.1uF capacitors on the P3.3V net and the PVDD net with a higher value like 10uF.

Q1:  Yes the conditions have a proportional relationship - use the 66 MHz information since your system is running at 60 MHz.

tDJIT information is in the Serializer Switching Characteristics on page 4 and shown in Figure 17 on page 10. 

Q2: There is no PRBS generation capability.  Only a sync signal can be generated by the LV!* on the output.

Regards,

Lee

Lee-san

Thank you for quick reply.

About signal generate;
If no PRBS generation, which pattern is DS92LV18 measure?
Customer is thinking that a repeat "01" and "10" pattern, is it OK?

Best regards,
Satoshi

Satoshi-san,

A repeating 01 and 10 pattern is not good for the DS92LV18 to lock correctly.  I cut out some information from page 13 in the datasheet.

If a specific pattern is repetitive, the Deserializer’s PLL will not lock in order to prevent the Deserializer from locking to the data pattern rather than the clock. We refer to such pattern as a repetitive multi-transition, RMT. This occurs when more than one Low-High transition takes places in a clock cycle over multiple cycles. This occurs when any bit, except DIN 17, is held at a low state and the adjacent bit is held high, creating a 0-1 transition. The internal circuitry accomplishes this by detecting more than one potential position for clocking bits. Upon detection, the circuitry will prevent the LOCK output from becoming active until the RMT pattern changes. Once the RMT pattern changes and the internal circuitry recognizes the clock bits in the serial data stream, the PLL of the Deserializer will lock, which will drive the LOCK output to low and the output data ROUTn will become valid.

If possible I would attempt to use the SYNC signal to lock and align the DS92LV18 SerDes.

Regards,

Lee

Lee-san

Sorry for many additional question for DS92LV18.
Please let me know about below points.

①About previous answer for tRMNI-Right and tRMHI-Left
　Are these spec really proportional relation?
　If proportional relation is correct, Sampling Window on 60MHz condition is very narrow.
　※60MHz tRMNI-Right → 334ps and tRMHI-Left → 462ps
　　Sampling window: 15MHz → 383ps, 66MHz → 248ps, 15MHz → 37ps

②About tDJIT spec
　On the datasheet figure17, are bit start and bit stop same spec?
　If 66MHz condition, I think that bit start's positive deterministic jitter (+) is 40ps and negative deterministic jitter (-) is 70ps, is it correct?
　And, datasheet is described 15MHz and 66MHz spec, is tDJIT proportional relation?
　(I want to know 60MHz condition)

③PRBS pattern
　・Customer want to get simply waveform data, this case only unnecessary Lock.
　　Is waveform different in the condition of Lock and Unlock?
　・If there data for eye pattern on any document, please let me know about condition for test pattern (or PRBS version, etc).

Best regards,
Satoshi

Satoshi,

Using the datasheet 66MHz information

Noise Margin Right = 180ps / 757 ps = 0.237 UI   ;   Noise Margin Left = 330 ps / 757 ps = 0.436 UI

For 60 MHz; 1.00 UI = 833.3ps

Noise Margin Right = 0.237UI x 833ps = 197ps   ;   Noise Margin Left = 0.436UI x 833ps = 363ps

For tDJIT the 66MHz condition is -70ps to +40ps for a total of 110ps.

Using the 66 MHz data, -70ps x 833ps/757ps = -77ps    and     40ps x 833ps/757ps = 44ps   for a total of 121ps.

There is no capability to produce a PRBS pattern from within the transmitter. 

Regards,

Lee