Team,
My customer has a question on the DP83867E as follows:
I have another question related to clocking for SGMII. It looks like our MAC (Xilinx ZU9 IP Core, MPSoC Ultrascale +) requires 125 MHz on a pair of differential clock inputs (mgt_clk_p / mgt_clk_n ) for Ethernet regardless of mode (SGMII, RGMII etc.). It looks like the DP83867E only sources 625 MHz in SGMII mode so our clock would need to be from a different external source other than the PHY. Is this correct or are there other options? The PHY single ended RX_CLK only works in RGMII mode and is speed dependent, correct ? (25MHz for 10/100 and 125MHz for 1000MHz).
I’m trying to nail down the various clocking requirements for both RGMII mode and SGMII mode,
we have a need for a fixed 125MHz clock output to the Xilinx SGMII core reference clock.
This description below from the TI DP83867E data sheet (section 9.seems to indicate there is no way to “fix” the clock output pin to 125MHz independent of the 10/100/1000 receive data rate (only 125MHz at 1000Mbps). Could you confirm there is no other way to generate a 125MHz output for the clock independent of data rate? We have a very stable 25MHz oscillator for the PHY and would like to use the PHY clock output for 125MHz output if there is a possible way.
9.3.3 Clock Output
The DP83867 has several internal clocks, including the local reference clock, the Ethernet transmit clock, and the
Ethernet receive clock. An external crystal or oscillator provides the stimulus for the local reference clock. The
local reference clock acts as the central source for all clocking in the device.
The local reference clock is embedded into the transmit network packet traffic and is recovered from the network
packet traffic at the receiver node. The receive clock is recovered from the received Ethernet packet data stream
and is locked to the transmit clock in the partner.
Using the I/O Configuration register (address 0x0170), the DP83867 can be configured to output these internal
clocks via the CLK_OUT pin. By default, the output clock is synchronous to the X_I oscillator / crystal input. The
default output clock is suitable for use as the reference clock of another DP83867 device. Via registers, the
output clock can be configured to be synchronous to the receive data at the 125-MHz data rate or at the divide
by 5 rate of 25 MHz. It can also be configured to output the line driver transmit clock. When operating in
1000Base-T mode, the output clock can be configured for any of the four transmit or receive channels.
Thanks,
Aaron
