A customer has an inquiry on the timing specs of the DP83848YB. See below.
I have some questions regarding timing specs in the DP83848YB datasheet. 1) The timing specs T2.4.1 and T2.5.1 for TX_CLK and RX_CLK high/low time of 16ns to 24ns, could this vary this much from cycle to cycle or would it be the same from cycle to cycle? For example if the current cycle is 16ns, could the next cycle be 24ns? 2) Also, I don't see any timing specs on period jitter for TX_CLK and RX_CLK. Would it be the same as the input jitter on the oscillator connected to X1? For example, if the oscillator we are using has 20psec of peak to peak period jitter, should we therefore add 20ps of period jitter to TX_CLK and RX_CLK? 3) Also, the setup, hold, and output delay timing specs for MII, do these timing specs already account for period jitter on TX_CLK and RX_CLK, assuming we are meeting the 25MHz oscillator spec of less than 800psec of input jitter?
