• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 32 subscribers
  • Views 686 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN65LVDM051: SN65LVDM051P not sexy signal on LVDS bus

eduard sajmir
Prodigy 10 points
Part Number: SN65LVDM051
Other Parts Discussed in Thread: DS90LV012A

Hi folks,

I would like to spread SPI interface from one Master card to 4 slave cards using LVDS bus. My problem is that communication is not reliable enough even CLK frequensy is 12MHz only.

I checked out main signals on the bus (differential input to LVDS receiver) and behind LVDS receiver (logical level).

LVDS driver: SN65LVDM051P 1ea

LVDS receiver: DS90LV012A 4pcs

Terminantion: PCB is designed according characteristic impedance

The curves:

card 1:

card 2:

description:

Cyan: CLK logical output from LVDS receiver

Yellow: MISO logical output from LVDS receiver

Violet: MISO differential LVDS signal on the bus. This is what makes me new wrinkles.

My question is WHY is shape of MISO signal on LVDS side so lazy and no sexy?

Looking forward to any help or advice.

  • 0
    TI__Mastermind 43795 points

    Hi Eduard,

    Can you draw the 1 driver to 4 receiver topology in more detail to show termination(s) and probe point of the Violet signal. 

    When LVDS generally works best as a point to point solution (one driver - one receiver).  The extra loading is causing some non-ideality in the receiver waveforms.  It is likely that the waveform at each receiver would look different.

    It is also interesting that the LVDS output is a 2Vpp signal.  This is more amplitude than we typically see from the driver.

    Regards,

    Lee