Team,
My customer has the following question:
At this point I’m using the DP83867E clk_out pin for a fixed 25MHz copy of the input clock on one of the DP83867E devices and generating the125MHz clock elsewhere.
Could you confirm the following default operation for clk_out is correct ? Also, which strap pin is used for the clock_out disable? It’s not clear in the datasheet.
From section 9.3.3 of the data sheet:
Using the I/O Configuration register (address 0x0170), the DP83867 can be configured to output these internal
clocks via the CLK_OUT pin. By default, the output clock is synchronous to the X_I oscillator / crystal input. The
default output clock is suitable for use as the reference clock of another DP83867 device.
Regards,
Aaron
