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DS90UB947-Q1: Repeater configuration - last receiver does'nt lock

Michael Chan70
Prodigy 80 points
Part Number: DS90UB947-Q1

Hi E2E members,

I got link-3 parts, 947 and 948 EVM,  connected and it works fine. No hop.

In my application I need 1 hop so I add one more 947/948 in the middle.

It doesn't lock well. It seems the jitter accumulate. Is there any app note to describe how to play with the jitter and pll loop bandwidth?

Many many Thanks.

Mike

  • 0
    Prodigy 80 points
    Hi Everyone,

    Is there anyone can comment? Or is there a deeper document that needs NDA?

    Thanks,
    Mike
  • 0 in reply to Michael Chan70
    TI__Genius 14015 points
    Hi Mike,

    There are no other documents explaining this mode. You are right that the jitter accumulates as it propagates along each hop.

    What PCLK frequency are you running? What type/length of cable are you using? What does the OLDI connection in between the repeater 948/947 look like? Are they mounted on the same board, or is there a ribbon cable?

    Thanks,
    Jason
  • 0 in reply to Jason Blackman
    Prodigy 80 points

    Hi Jason,

    Thank you so much for your reply.

    The PCLK is 140MHz. It does lock better when I switched to test pattern generator with internal clock 100MHz at the 1st TX. So it makes sense  that the SI is function of PCLK and cable length.  We used 14m cat6a cable between 1st TX and 1st RX. 2m between 2nd TX and 2nd RX.   Since we are evaluating the system using EVMs, the OLDI in the repeater is a shielded impedance-matched cable which was originally used in a display panel. The cable is directly soldered onto the 947 and 948 EVMs. The length of the OLDI cable is just about 5". I didn't use ribbon cable because I thought it is hard to find a good high speed ribbon cable. Any comment to improve this current configuration is highly appreciated.

    Thanks,

    Michael