DP83848I: How is CLKOUT pin signal output when X1 is High-impedance or Low?

Hi,

My customer said:
When XI pin is high-impedance, CLK_OUT signal is 170MHz clock output.
When XI pin is Low. CLK_OUT signal is 6MHz clock output.
(They took the signal waveform and sent me it. It can not attach the file. It's customer data)

My customer would like to know about the CLK_OUT signal(25-pin) when an abnormality occurs.
So, They'd like to know whether this is an assumed operation. Is this correct operation?

Also, can you answer this?
I understand X1 Clock must be stable before power-up and this goes out the operation guaranteed range.
So, I know you may not answer this.
If possible, would you please let me know that? This is requesting from my customer.


Best Regards,
Takahiro Ogo