Hi Team,
My customer want to know how the delay from GPIOX down edge to GPIOY up edge when changing PDO. They are using 4 GPIO to switch DCDC converter's enable pin and they want to make sure seamless voltage level switching by TPS65982's GPIO control.
Please tell me about the following two points to close their questions..
1. Is there a possibility that an overlap period occurs between GPIO signals when PDO is changed as below?
2.If it's not, How much delay does the GPIO have from down edge?
I need to answer this questions by March 8th, JST. so I would like to have any response as soon as possible
Regards,
Takashi Onawa