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SN75DPHY440SS: DA0P Lane not Passing HS Data

Franz Dill
Prodigy 20 points
Part Number: SN75DPHY440SS

I'm utilizing the SN75DPHY440SS in 4 lane configuration with default configuration parameters, sourced by a CSI-2 source.  Lanes 1, 2, and 3 are correctly driven and re-drive both LP and HS signals.  

Lane 0 is driven by the same source but fails to pass HS data (oddly, LP data is being passed correctly).

This "shouldn't" matter, but we are NOT abiding by lane ordering (i.e. MIPI lane 4 passes through DA0P/DA0N) - per the datasheet, that's acceptable.

Source receiver and termination is identical for each lane.

Any thoughts or similar experiences?

8.2 Typical Application, CSI-2 Implementations The DPHY440 supports 4 CSI-2 DPHY lanes plus a clock. Unlike DSI, CSI-2 does not have a back channel path. Because of this, there is no requirement on lane ordering. Because there is no lane ordering requirement, there are more combinations which can be implemented. All possible combinations are supported by the DPHY440. For all CSI-2 implementations, the polarity must be maintained between the CSI-2 Source and CSI-2 Sink. The DPHY440 does not support polarity inversion

  • 0
    TI__Mastermind 18655 points

    Hello Franz,

    Sorry for the delay in our reply. DPHY440’s LP TX is expecting to connect to an unterminated LP RX.  With Lane 0 path (DA0P/N and DB0P/N) supporting bi-directional LP signaling, it is very important that DB0P/N LP TX is connected to an unterminated LP RX.  If DB0P/N LP TX is connected to a HS RX, then LP signaling will not be able to reach the LP11 levels and which will cause the DPHY440 to not enable HS data path on Lane0.

    Try following for enabling lane0 HS path:

    Enable HS path for Lane 0 only:

    Write Register 0x50 with 8’h01 //Override enable for HS TX path

    Write Register 0x51 with 8’h01 //HS TX path enabled.

    Write Register 0x61 with 8’h00  // Disable LP path.

    Write Register 0x70 with 8’h01  //Override enable for HS RX path

    Write Register 0x71 with 8’h01  // HS RX path enabled.


    Bit 0 is lane 0

    Regards

  • 0 in reply to Joel Jimenez0
    Prodigy 20 points

    Joel,

    Thanks for your response.  The design does have non-standard LP RX on lane 0.  A variation of the settings provided the perfect solution.  Thank you for your assistance!