Linux/SN65DSI83: 0

Jerry Chiu

Part Number: SN65DSI83

Tool/software: Linux

Hi,

We are trying to enable "Test Pattern" function of SN65DSI83 IC in our device and seems no data output from SN65DSI83 (LCD panel is still white screen).

Here are questions:

1. Could anyone tell us what kind of pattern will output from SN65DSI83 if "Test Pattern" function enabled successfully?

2. Below is our setting for configuring SN65DSI83, could anyone help to check if any step we miss or did wrong? Thanks.

//Soft reset and disable PLL
    i2c_smbus_write_byte_data(dsi65_i2c_dev->client, SN65DSI83_SOFT_RESET, 0x01);
    i2c_smbus_write_byte_data(dsi65_i2c_dev->client, SN65DSI83_PLL_EN, 0x00);

    //select LVDS piexl clock form REFCLK and Range 62.5MHz - 87.5MHz
    i2c_smbus_write_byte_data(dsi65_i2c_dev->client, SN65DSI83_CORE_PLL, 0x04);

//multiply REFCLK by 3.
i2c_smbus_write_byte_data(dsi65_i2c_dev->client, SN65DSI83_PLL_DIV, 0x02);

    //four DSI lanes with single channel
    i2c_smbus_write_byte_data(dsi65_i2c_dev->client, SN65DSI83_DSI_CFG, 0x20);
    i2c_smbus_write_byte_data(dsi65_i2c_dev->client, SN65DSI83_DSI_EQ, 0x00);

    //set DSI clock range 450MHz - 455MHz
    i2c_smbus_write_byte_data(dsi65_i2c_dev->client, SN65DSI83_CHA_DSI_CLK_RNG, 0x5A);

//set LVDS for single channel, 24 bit mode, HS/VS low, DE high
i2c_smbus_write_byte_data(dsi65_i2c_dev->client, SN65DSI83_LVDS_MODE, 0x78);

    //set LVDS 100 Ohm termination and max differential swing voltage
    i2c_smbus_write_byte_data(dsi65_i2c_dev->client, SN65DSI83_LVDS_SIGN, 0x00);
    i2c_smbus_write_byte_data(dsi65_i2c_dev->client, SN65DSI83_LVDS_TERM, 0x02);

    //x resolution high/low for channel A 1366
    i2c_smbus_write_byte_data(dsi65_i2c_dev->client, SN65DSI83_CHA_LINE_LEN_LO, 0x56);
    i2c_smbus_write_byte_data(dsi65_i2c_dev->client, SN65DSI83_CHA_LINE_LEN_HI, 0x05);

    //y resolution high/low for channel A 768
    i2c_smbus_write_byte_data(dsi65_i2c_dev->client, SN65DSI83_CHA_VERT_LINES_LO, 0x00);
    i2c_smbus_write_byte_data(dsi65_i2c_dev->client, SN65DSI83_CHA_VERT_LINES_HI, 0x03);

    //SYNC delay high/low for channel A
    i2c_smbus_write_byte_data(dsi65_i2c_dev->client, SN65DSI83_CHA_SYNC_DELAY_LO, 0x00);
    i2c_smbus_write_byte_data(dsi65_i2c_dev->client, SN65DSI83_CHA_SYNC_DELAY_HI, 0x02);

    //HSYNC width high/low for channel A 14
    i2c_smbus_write_byte_data(dsi65_i2c_dev->client, SN65DSI83_CHA_HSYNC_WIDTH_LO, 0x0E);
    i2c_smbus_write_byte_data(dsi65_i2c_dev->client, SN65DSI83_CHA_HSYNC_WIDTH_HI, 0x00);

    //VSYNC width high/low for channel A 3
    i2c_smbus_write_byte_data(dsi65_i2c_dev->client, SN65DSI83_CHA_VSYNC_WIDTH_LO, 0x03);
    i2c_smbus_write_byte_data(dsi65_i2c_dev->client, SN65DSI83_CHA_VSYNC_WIDTH_HI, 0x00);

//Horizontal BackPorch for channel A 30
i2c_smbus_write_byte_data(dsi65_i2c_dev->client, SN65DSI83_CHA_HORZ_BACKPORCH, 0x1E);

//Vertical BackPorch for channel A 15
i2c_smbus_write_byte_data(dsi65_i2c_dev->client, SN65DSI83_CHA_VERT_BACKPORCH, 0x0F);

//Horizontal FrontPorch for channel A 150
i2c_smbus_write_byte_data(dsi65_i2c_dev->client, SN65DSI83_CHA_HORZ_FRONTPORCH, 0x96);

    //Vertical FrontPorch for channel A 20
    i2c_smbus_write_byte_data(dsi65_i2c_dev->client, SN65DSI83_CHA_VERT_FRONTPORCH, 0x14);
    i2c_smbus_write_byte_data(dsi65_i2c_dev->client, SN65DSI83_TEST_PATTERN, 0x11);
    //Soft reset and enable PL
    i2c_smbus_write_byte_data(dsi65_i2c_dev->client, SN65DSI83_SOFT_RESET, 0x00);
    i2c_smbus_write_byte_data(dsi65_i2c_dev->client, SN65DSI83_PLL_EN, 0x01);

over 8 years ago

0 Joel Jimenez0 over 8 years ago

TI__Mastermind 18655 points

Hello Jerry,

Could you share the panel's datasheet?

Is the LVDS CLK output running correctly? Correct levels, frequency, no jitter?

Regards

0 Jerry Chiu over 8 years ago in reply to Joel Jimenez0

Prodigy 40 points

Hello Joel,
Thanks for your quick response.
I am new in this forum and I am not sure if it's possible to attach panel's datasheet in the forum.
Could you provdied your e-mail so that I can send datasheet to you?
I will check LVDS CLK and other signal per your comment later.

0 Joel Jimenez0 over 8 years ago in reply to Jerry Chiu

TI__Mastermind 18655 points

Hello Jerry,

Please, send a email to joel.jimenez@ti.com

Regards

0 Jerry Chiu over 8 years ago in reply to Joel Jimenez0

Prodigy 40 points

Hello Joel,

I alredy sent datasheet and our current LVDS configurations to your mail address.

Currenlty, we can see test pattern output in LCD panel.

However, when we disable test pattern function and change input source to SOC DSI, no image output in LCD panel.

Is there any registers related to SOC DSI input we need to modify?

0 Joel Jimenez0 over 8 years ago in reply to Jerry Chiu

TI__Mastermind 18655 points

Hi Jerry,

Did you change anything in your register config to see the test pattern?

Please, try this configuration and let me know if it works for the test pattern mode.

For normal operation, verify that you have the MIPI inputs driven to LP11(both P and N pairs of all MIPI DSI differential pairs to single ended high ~1.2V) prior to asserting EN pin as stated in the datasheet init sequence.

Check the status of the error register 0xE5.

Fullscreen CSR.txt Download

//=====================================================================
// Filename   : CSR.txt
//
//   (C) Copyright 2013 by Texas Instruments Incorporated.
//   All rights reserved.
//
//=====================================================================
0x09              0x00
0x0A              0x04
0x0B              0x02
0x0D              0x00
0x10              0x26
0x11              0x00
0x12              0x5a
0x13              0x00
0x18              0x78
0x19              0x00
0x1A              0x03
0x1B              0x00
0x20              0x56
0x21              0x05
0x22              0x00
0x23              0x00
0x24              0x00
0x25              0x03
0x26              0x00
0x27              0x00
0x28              0x20
0x29              0x00
0x2A              0x00
0x2B              0x00
0x2C              0x0e
0x2D              0x00
0x2E              0x00
0x2F              0x00
0x30              0x03
0x31              0x00
0x32              0x00
0x33              0x00
0x34              0x1e
0x35              0x00
0x36              0x0f
0x37              0x00
0x38              0x96
0x39              0x00
0x3A              0x14
0x3B              0x00
0x3C              0x10
0x3D              0x00
0x3E              0x00


The PLL_EN bit and SOFT_RESET bit are not set as they need to be set per the recommended sequence defined in the datasheet

Regards

0 Jerry Chiu over 8 years ago in reply to Joel Jimenez0

Prodigy 40 points

Hello Joel,

We can see OS home screen output in LCD panel now.

The problem is related to the sequence between Bridge IC initialization and SOC display subsystem initialization.

Thanks for your comment~

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Linux/SN65DSI83: 0