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SN65DSI84: why does new pixel data seem to change in the middle of a clock

Eric Steimle
Expert 2300 points

Part Number: SN65DSI84

If I look at page 17 figure 11 it seems to show that new pixel data comes out 90 degrees from the rising clock edge.  Is this true?  Why is that?  I would have expected the start of the serial pixel stream to be edge aligned, although I could see how having that delay could help the design of the chip I guess.

  • 0
    TI__Mastermind 18655 points

    Hi Eric, 

    Per standard, the rising edge of the LVDS clock occurs two LVDS sub-symbols before the current cycle of data. The clock is compose of a 4 LVDS sub-symbol HIGH time and a 3 LVDS sub symbol LOW time.

    The LVDS output timing parameters are stated in the 6.6 Switching Characteristics.

    Regards