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DS90UH948-Q1: I have a question is Deserializer LVDS Transmitter.

BJ Han
Expert 2035 points
Part Number: DS90UH948-Q1

Hi TI,

Thank you for your attention and support.

I have a question is Deserializer LVDS Transmitter(DS90UH948-Q1).

1. Spec requirements.
- 2M (1080P) 60 fps available
- LVDS input / output possible
- The Pakage Size is similar to the existing one (DS90UB913Q / 914Q)
- Sensor SPI / I2C communication channel connection possible

2. I chose two products below.

-. Serializer : DS90UH947-Q1

-. Deserializer : DS90UH948-Q1

3. Question

=> The first page of the datasheet says that it is possible to input a pixel clock of 170mhz, but the AC timing shows that it is only 85Mhz.
For 1080p60fps, the LVDS clock is 111.375Mhz. (-> data is 8 lane)

Can it be used according to Spec?

Thank you.


  • 0
    TI__Expert 3245 points
    Hi BJ,

    Please refer to section 8.4 of the DS90UB948 datasheet, regarding modes of operation:

    8.4.1.4 2-lane FPD-Link III Input, Single Link OpenLDI Output
    In this configuration the PCLK rate embedded within 2-lane FPD-Link III frame can range from 50 MHz to 170
    MHz, resulting in a link rate of 875 Mbps (35 bit * 25 MHz) to 2.975 Gbps (35 bit * 85 MHz). Each LVDS data
    lane will operate at a speed of 7 bits per LVDS clock cycle; resulting in a serial line rate of 350 Mbps to 1190
    Mbps. CLK1 will operate at the twice the rate as PCLK with a duty cycle ratio of 57:43.

    The AC timing is referring to a maximum single lane rate of 85MHz, the Pixel Clock can be up to 170MHz but will be split across 2 lanes( eg 2 x 85MHz = 170MHz).

    Regards,