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DS32EL0124: Error monitoring and register definitions

sanjay parekh
Prodigy 180 points

Part Number: DS32EL0124

Hello,

 

I am trying to make sense of the error monitor registers in DS32EL0124 Deserializer device. Some other engineers may also have been in touch with you regarding this.

 

We are operating the Serializer and Deserializer with bootstrapped {RS,DC_B} = {1,0} i.e. Remote sensor disabled and DC Balance enabled.   In this premise, please see my questions below –

 


  1. What is the difference between CDR Event Counter and Data Event Counter? Is the Data Event counter same as Data Error Counter? If yes! What is the difference between Event counter read out by registers 0x3D and {0x3F,0x3E}?
  1. In the above picture of Reg 0x2B I am assuming that writing 1 to reset bits clear the counters where as writing 1 to the enable count disables event counters.
  2. Again in Reg 0x2B, are the reset bits self clearing?

  3. In register 0x2D, what is the definition of “Current Run” and “Selected timing Window?”
  1. In Reg 0x2D, what is the definition of “Current and Previous State of Errors?”
  2. In Reg 0x2D, what does counting accumulation do? I suspect it has something to do with the definitions of current and previous states.

 

One additional clarification I need regarding status indicated by the LOCK pin and the RxOUT4+/- when DC Balance is enabled and Remote Sense is turned off. Quoting the DS32EL0124 datasheet –

“If RxOUT4+/- is low, then the data output from RxOUT0 - RxOUT3 has been successfully decoded using the 8b/10b coding scheme. If RxOUT4+/- is high and the outputs RxOUT0 - RxOUT3 are high then an invalid 8b/10b code was received, signifying a bit error. If RxOUT4+/- is high and the outputs RxOUT0 - RxOUT3 are low then an idle character has been received.”

Can you please help me populate and or correct the following truth table. I see the following in the datasheet.  

LOCK

RxOUT4+/-

RxOUT[3:0]+/-

Description

LOW

LOW

X

CDR is locked.   8b/10b successfully decoded.

LOW

HIGH

LOW

What does this mean? Should we never expect this? If it indicates an error condition, which register will let us monitor these events?

LOW

HIGH

HIGH

CDR is locked. Invalid 8b/10b code received. Which register will show error count? In register 0x2B do I have to select CDR event counter or Data Error Counter to see these errors?

HIGH

x

x

CDR is unlocked. Which register will monitor these error? I suspect register 0x2B CDR events. After this event, if we make the serializer send K codes, we see the status change to LOW. Does this event get indicated in the registers anywhere?

 

 

  • 0
    TI__Intellectual 1470 points
    TSR - Subbing to this thread
  • 0
    TI__Intellectual 1635 points
    Hi Sanjay,
    Sorry for the delay in response, I just located an EVM to verify your questions. I'm still in the middle of testing, but wanted to get you an update while I continue to verify functionality.

    1.
    What is the difference between CDR Event Counter and Data Event Counter? Is the Data Event counter same as Data Error Counter? If yes! What is the difference between Event counter read out by registers 0x3D and {0x3F,0x3E}?
    [RH] I can verify that when CDR Event Counter is selected in 0x2B, any CDR events will be counted in the Event Status register 0x3D. At this time, I have not been able to create a Data Event or Data Error to validate which register this will log this event/error. I will provide an update once I generate a data event/error.

    1.In the above picture of Reg 0x2B I am assuming that writing 1 to reset bits clear the counters where as writing 1 to the enable count disables event counters.
    [RH] Writing a '1' to Reset CDR Error Count and Reset Link Error Count in Reg 0x2B will clear the counters. Writing a '1' to Enable Count will enable the event counter.

    2.Again in Reg 0x2B, are the reset bits self clearing?
    [RH] Yes, the reset bits are self-clearing in Reg 0x2B.

    3.
    In register 0x2D, what is the definition of “Current Run” and “Selected timing Window?”
    1.In Reg 0x2D, what is the definition of “Current and Previous State of Errors?”
    2.In Reg 0x2D, what does counting accumulation do? I suspect it has something to do with the definitions of current and previous states.
    [RH] I am still working to answer the rest of your questions. As stated earlier, I have not been able to generate any data events/errors, so I have not been able to verify this functionality. I will continue to work on the EVM and provide updates.

    Regards,
    Ryan