Hello,
There is a phenomenon that the PCLK changes by changing the GPO pin [1: 0] of the DS90UB913A-Q1 in the customer.
They created a program that intentionally changes the state of GPO [1: 0] in about 0 ms to 2 ms after PDB goes high, and checked the operation.
As a result, they were able to confirm the change in output PCLK of 914A.
The GPO [1: 0] pins depend on the external pull-up and pull-down resistors in the TRI-STATE state until tPLD is determined as shown in the data sheet in Figure 9.
After that, it became low output once, then it became the operation which determined the Output level (High / Low) depending on the state of 914.
Is there a pin you are checking at the timing when the PLL of the serializer locks since PDB goes high?
Best Regards,
Ryuji
